1. Katholieke Hogeschool Kempen VHDL package 1 Package Basic functions in library

2. Katholieke Hogeschool Kempen VHDL package 2 Library IEEE Std_logic is gedefinieerd in het package: o “ieee.std_logic_1164” Dit package zit in de library : o “library IEEE” Oproepen van verschillende Packages uit library IEEE o library ieee; o use ieee.std_logic_1164.all; (standaard data types) o use ieee.std_logic_arith.all; (rekenkundige bewerkingen)

3. Katholieke Hogeschool Kempen VHDL package 3 Package declaration -- Package declaration package name_of_package is package declarations end package name_of_package;

4. Katholieke Hogeschool Kempen VHDL package 4 Voorbeeld Package declaration library ieee; use ieee.std_logic_1164.all; package basic_func is -- AND2 declaration component AND2 port (in1, in2: in std_logic; out1: out std_logic); end component; -- OR2 declaration component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component; end package basic_func;

5. Katholieke Hogeschool Kempen VHDL package 5 Oproepen package Library ieee; use ieee.std_logic_1164.all; Library work; Use work. basic_func.all; o Work is de naam van het working library o Basic_func is het package in de library o.all wil zeggen dat we alles willen gebruiken uit dit package

6. Katholieke Hogeschool Kempen VHDL package 6 Overzicht package files “oefening auto alarm”.vhd file AND1.vhd file OR1.vhd file NOT1.vhd file test_package o Roept AND, OR, NOT op o Wordt bewaard in WORK library.vhd file warning1_package o Roept package (test_package) op uit work library

7. Katholieke Hogeschool Kempen VHDL package 7 voordeel De package hoeft niet in de zelfde map te staan als het top design

8. Katholieke Hogeschool Kempen VHDL package 8 Simpel voorbeeld LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY AND1 IS PORT( in1, in2: INSTD_LOGIC; out1: OUTSTD_LOGIC); END AND1; ARCHITECTURE a OF AND1 IS BEGIN out1 <= in1 and in2 END a;

9. Katholieke Hogeschool Kempen VHDL package 9 Voorbeeld met package.vhd file AND poort LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY AND1 IS PORT( in1, in2: INSTD_LOGIC; out1: OUTSTD_LOGIC); END AND1; ARCHITECTURE a OF AND1 IS BEGIN out1 <= in1 and in2 END a;

10. Katholieke Hogeschool Kempen VHDL package 10 Voorbeeld met package.vhd file package LIBRARY IEEE; USE IEEE.std_logic_1164.all; package test_package is component AND1 PORT( in1, in2: INSTD_LOGIC; out1: OUTSTD_LOGIC); end component; end test_package;

11. Katholieke Hogeschool Kempen VHDL package 11 Voorbeeld met package.vhd file top design LIBRARY IEEE; USE IEEE.std_logic_1164.all; Library work; use work.test_package.all; ENTITY warning1_package IS PORT( DOOR, IGNITION, SBELT: INSTD_LOGIC; WARNING1: OUTSTD_LOGIC); END warning1_package; ARCHITECTURE a OF warning1_package IS signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic; BEGIN U2: AND1 port map (IGNITION, DOOR_NOT, B1); U3: AND1 port map (IGNITION, SBELT_NOT, B2); end a;

12. Katholieke Hogeschool Kempen VHDL package 12 Oefening dobbelsteen Zie site.