1. Digital Techniques Fall 2007 André Deutz, Leiden University
Sequential Circuits
Prelim on delays and performance
Sequential circuits
CLU with feedback loops
Bi-stable (aka S-R flip-flop)
Next time:
Application of flip-flops
Clocked flip-flops, clocked D-flip-flops
Level-triggered, edge-triggered, master-slave flip-flops
Digital Techniques Fall 2007 André Deutz, Leiden University

2. The Inverter at the Transistor Level( a ) b c d A B s e E m i t r C o l G N D = V + 5 4 . 3 2 1 6 8 n – I p u v g O R L W
Power
terminals
Transistor
symbol
A transistor used
as an inverter
Inverter transfer
function
(Compare to our relay implementation of the inverter.)

3. Assignments of Logical 0 and Logical 1 to Voltage Ranges+ 5 V + 5 V L o g i c a l 1 L o g i c a l 1 2 . 4 V 2 . V F o r b i d d e n r a n g e F o r b i d d e n r a n g e . 8 V . 4 V L o g i c a l V V L o g i c a l
(a) At the output of a logic gate
(b) At the input to a logic gate

4. Assignments of Logical 0 and Logical 1 to Voltage Ranges+ 5 V + 5 V L o g i c a l 1 L o g i c a l 1 2 . 4 V 2 . V F o r b i d d e n r a n g e F o r b i d d e n r a n g e . 8 V . 4 V L o g i c a l V V L o g i c a l
(a) At the output of a logic gate
(b) At the input to a logic gate

5. Speed and Performance The speed of a digital system is governed by
the propagation delay through the logic gates and
the propagation across interconnections.

6. Propagation Delay for a NOT Gate
Transition Time + 5 V
The NOT
Output changes
From 1 to 0
(Fall time) 1 % 5 % ( 2 . 5 V ) 9 % V
Propagation Delay
(Latency)
Transition Time + 5 V
The NOT
Output changes
From 0 to 1
(Rise time) 9 % 5 % ( 2 . 5 V ) 1 % V
Time

7. Digital Techniques Fall 2007 André Deutz, Leiden University
If you don’t believe in delays: think again (“nothing” is instantaneous)
Switches in series => AND
Input 1
Input 2
Current / no current
Digital Techniques Fall 2007 André Deutz, Leiden University

8. Sequential Logic
The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs.
There is a need for circuits with a memory, which behave differently depending upon their previous state.
An example is the vending machine, which must remember how many and what kinds of coins have been inserted, and which behave according to not only the current coin inserted, but also upon how many and what kind of coins have been deposited previously.
These are referred to as finite state machines, because they can have at most a finite number of states.

9. Classical Model of a Finite State Machinek S y n c h r z a t s g l f e b m C u Q D ( p ) I O
. . .
. . .
. . .
. . .
. . .

10. Feedback paths in a logic circuitY X Y X Z
Digital Techniques Fall 2007 André Deutz, Leiden University

11. Feedback paths in a logic circuitQ A B F 1 1 1 1 1 1 A F = A + B B
NOR

12. S-R flip-flop (aka bi-stable)
In which state can the S-R flip-flop be?
S=0 & R=0
Q=0, Q` = 0 ?
Q=0, Q` = 1 ?
Q=1, Q` = 0 ?
Q=1 , Q` =1 ?
S=0 & R=1
Digital Techniques Fall 2007 André Deutz, Leiden University

13. S-R flip-flop (aka bi-stable)
In which state can the S-R flip-flop be?
S=1 & R=0 (use symmetry)
Q=0, Q` = 0 ?
Q=0, Q` = 1 ?
Q=1, Q` = 0 ?
Q=1 , Q` =1 ?
S=1 & R=1
Digital Techniques Fall 2007 André Deutz, Leiden University
Digital Techniques Fall 2007 André Deutz, Leiden University

14. S-R flip-flop (aka bi-stable)
S and R are predominantly 0
Summary: When setting S to 1 momentarily, the latch ends up in state Q=1, regardless of the previous state; when S drops back to 0 state will stay Q=1. Likewise, setting R to 1 momentarily forces the latch to Q=0. (When R=S=0, then Q=1 or Q=0 (both are stable) – if you never allow R=S=1, then Q=1 in case S was the most recent input set to 1; otherwise R was the most recent input set to 1.
Thus S-R is a rudimentary 1-bit memory
S == set; R == reset (aka clear)
We have tacitly assumed that the NOR gate has delays!
State S=R=1 and Q=Q’=0 is stable – one of the troubles with this is that we cannot predict anymore what happens when S and R return to 0.
Digital Techniques Fall 2007 André Deutz, Leiden University

15. A NOR Gate with a Lumped DelayB 1 D t +
Timing behavior
This delay between input and output is at the basis of the functioning the flip-flop (= important memory element)

16. An S-R Flip-Flop (a bi-stable)Q R T i m n g b e h a v o r 2 D t + 1 ( d s l w )
The S-R flip-flop is an active-high (positive logic) device.

17. Digital Techniques Fall 2007 André Deutz, Leiden University

18. Converting a NOR S-R to an NAND S-R
Active-high
NOR Implementation
Push bubbles
(DeMorgan’s)
Rearrange
bubbles
Convert
from bubbles
to active-low
signal names

19. A Circuit with a Hazard It is desirable to be able to “turn off”Q R T i m n g b e h a v o r 2 D t G l c u s d y z
It is desirable to be able to “turn off”
the flip-flop so it does not respond to
such hazards.

20. A Clock Waveform
In a positive logic system, the “action” happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock next goes high.

21. A Clocked S-R Flip-FlopQ R T i m n g b e h a v o r 3 D t 2
The clock signal, CLK, turns on the inputs to the flip-flop.

22. A Clocked D (Data) Flip-FlopS y m b o l Q i r c u t T n g e h a v 2