1. Boolean Algebra Variables: only 2 values (0,1)
Huntington’s (1804) axioms:
1 1 = = 0
a 0 = a + 1 = 1
a a’ = a + a’ = 1
a b = b a a + b = b + a
a(b+c)=ab+ac a+bc=(a+b)(a+c)
Verification by truth table:
abc (a+b)c ac+bc
Application to electric switches (open - 0, closed - 1): a L c
220V~ b
L = (a + b)c = ac + bc a c L
220V~ b c
L = ac + bc
Every logical function can be specified by truth table and
implemented as sum of product form,e.g. L = a’bc + ab’c + abc.

2. Combinational Circuits
Output is direct function of inputs a a’
NOT
Switch light L implemented by gates
L = a’bc + ab’c + abc sum of products. a b
a+b
a b c L OR a b ab
Function presentation by Karnough map
every product term has a field, and neighboring
fields differ by only one variable.
Example (three input variables):
L = abc + ab’c + a’bc
= abc + ab’c + abc + a’bc
= ac(b + b’) + bc(a + a’)
= ac + bc
= (a + b)c b a 1 1 c a
a+b 1 b L c L

3. Decoders and Multiplexers
Decoder has n inputs and 2n outputs: A B BA
Mux determines which input will connect to output:
A B C D
A B C D 1 1 1 1
S[1:0] 2 S 1
OUT
OUT

4. Binary Adder Design a0 a3 a2 a1 b3 b2 b1 b0 c3 c2 c1 c0 c4 s3 s2 s1 s0co ci
a b ci s co
Truth Table
a b ci s co
Karnough maps a b ci a b ci 1 1 1 1 1 1 1 1
s = ab ci +ab ci’
+a’b’ ci +a’b’ ci’=
(ab + a’b’)ci +
(ab + a’b’)ci’ =
(a + b’) + ci =
a + b’ + ci
co = ab + aci + bci

5. Programmable Logic Arrays PLA
Any logical function can be implemented by two levels circuits: ANDs and ORs. A B C X Y

6. Design of the RS flip-flopc b a p x 1 a: a: b: b: a b CC p c
a b p
stable x c b a x 1
p = a + b’c b’ p c a a b p’ a b p p
time

7. Registers One bit register = memory cell WE = Clock pulse in bit gate
out bit
Eight bit register b7 b6 b5 b4 b3 b2 b1 b0 WE

8. The Concept of Memory WE N address lines (bus) address space = 2N
Memory as array of registers: address space and addressability
address decoder
memory 0 WE
memory 1
memory 2
N address
lines (bus)
address
space = 2N
memory 3
memory 4
memory 5
memory 6
memory 7
M data lines (bus)

9. Memory details address word select word WE input bits write enable
Decoder asserts one of the word select lines, based on address.
Word select activates one of the output AND gates, which drives the selected data to the output OR gate. (For a read, this is basically a MUX -- decoder ANDed with signals, results ORed together.)
When writing, the only WE bits for the proper word are asserted (based on decoder again).
output bits

10. Design of the JK flip-flop
master
slave J A B Q Q’ A B K CL
B closes
A closes
A opens
master accepts
B opens
slave accepts
At no time the path between inputs JK and outputs QQ’ is closed.

11. Synchronous Sequential Circuit
Output
Input CC
Next
state
Present
state A B
clock
* Output is a function of Input and Present state.
* Next state is a function of Input and Present state.
* Present state is delayed Next state.

12. Traffic warning sign All off 1,2 on 00 01 10 11 0,1 1 1 2 3 4 5
1,2,3,4 00 01 10 11
0,1 1
1,2 1 2 3 4 5 SW SW
3,4
Combinational
Circuit 5 SW E1
E1+ E2
E2+
State
SW current next output
SW E1 E2 E1+ E2+ 1,2 3,4 5 Cl E1 E2
1,2
3,4 5
E1+
E2+ E1 E2 SW
E1+ = SW E1’ E2 + SW E1 E2’
E2+ = SW E1’ E2’ + SW E1 E2’
1,2 = E SW E1 E2
3,4 = E SW E1 E2
5 = SW E1 E2
Combinational
Circuit

13. Reversible counter modulo 5
000
110
010
011
001 1
a b c
Next State 1 x a b c I 1 x a b c I 1 x a b c I
a+ = a’bc’I’ + b’c’I
b+ = (c + a’b) I’ + c’I
c+ = ab’ + b’I’ + a’b I
a+ = a’bc’I’ + b’c’I
b+ = (c + a’b) I’ + c’I
c+ = ab’ + b’I’ + a’b I a+ b+ c+ a b c I CL