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April 30, 2014 1 A New Tool for Designer-Level Verification: From Concept to Reality April 30, 2014 Ziv Nevo IBM Haifa Research Lab
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April 30, 2014 2 Overview Designer-level verification (DLV) DLV tools: historical perspective at IBM Our latest recipe
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April 30, 2014 3 Designer-level verification (DLV)
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April 30, 2014 4 Life without DLV Logic designer Verification engineer spec----- ----- RTL
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April 30, 2014 5 Weeks later… Logic designer Verification engineer spec----- ----- fail trace
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April 30, 2014 6 DLV ≈ “ Developer testing ” (standard practice in SW) Verification engineer Logic designer RTL Basic checks
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April 30, 2014 7 What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification
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April 30, 2014 8 Verification: tools of the trade Simulator Testbench HVL Methodology Scripts Formal Assertions Coverage … Logic designer Verification engineer
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April 30, 2014 9 DLV: what should the tools be? Logic designer Simulator Testbench HVL Methodology Scripts Formal Assertions Coverage …
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April 30, 2014 10 DLV tools: historical perspective at IBM
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April 30, 2014 11 Idea 1: TIMEDIAG (1997) Specify input value/function/random Loop cycle (count/random/condition)
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April 30, 2014 12 Idea 1: TIMEDIAG (1997) GenRand Random instantiation Simulation Checking
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April 30, 2014 13 TIMEDIAG ingredients simulation Waveform- based interface complex interleavings What’s missing? Interactive define/run/view Event-guided test cases Formal analysis
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April 30, 2014 14 What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification
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April 30, 2014 15 Idea 2: PathFinder (2002) Define events View trace Find a trace (formal analysis)
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April 30, 2014 16 Idea 2: PathFinder (2002) Main flow: Specify events Find trace View trace Minor feature: Edit inputs on waveform Simulate
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April 30, 2014 17 PathFinder ingredients waveform- based interface simulation Interactive define/run/view Event- guided test cases Formal analysis What’s missing? Simple driving (default is random) Fast simulation Integration with common tools
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April 30, 2014 18 What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification
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April 30, 2014 19 Another DLV tool
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April 30, 2014 20 Jasper Visualize
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April 30, 2014 21 Our latest recipe
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April 30, 2014 22 Latest recipe: Diver Main flow Specify inputs Simulate View trace IBM Debug and Verification Tool for Designers (DIVER) scenario editor Specify expected results View unexpected results
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April 30, 2014 23 Latest recipe: Diver Additional variations Repetitions and delays Specify events on outputs Run-to-failure Simulate or run formal engine Assertions and coverage
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April 30, 2014 24 Debugging Import trace Trace from simulation of integrated component Scenario for designer-level component
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April 30, 2014 25 Diver ingredients simulation Waveform- based interface Interactive define/run/view Event- guided test cases Formal analysis Climate for DLV
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April 30, 2014 26 What activities does DLV include? Observing mainstream behavior Exploring corner cases Checking assertions and coverage points Bug hunting Debugging Observation Lightweight verification
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April 30, 2014 27 Conclusions DLV activity should scale linearly with the amount of effort spent Recommended recipe: – Waveform-based interface – Interactive define/run/view – Integration with common tools – Driving inputs – Simulation – Event-based test cases – A touch of formal analysis
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April 30, 2014 28 Questions?
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