1. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design WP3: Qualitative Fault Modelling András Pataricza, Professor Budapest University of Technology and Economics

2. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 2 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Qualitative Fault Modelling – Objectives  Exploratory study for test optimization  Identification of fault classes that have significant effects regarding dependability/safety requirements  Based on systematic modelling of faults  Addressing the model complexity problem  Qualitative abstraction: Aggregating states/values belonging to the same operational domain Spatial abstraction: Using error predicates Temporal abstraction: Using temporal predicates  Semi-decision supported by the abstract model Negative result is a proof of non-existence of critical faults Positive result shall be checked in the concrete model (TCG controlled by the analysis in the abstract model)

3. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 3 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Qualitative Fault Modelling – Progress  Demonstrating the abstraction method:  Modelling reference instance and mutations (failure modes)  Construction of composite automata  Signal level spatial compaction  Temporal compaction  Demonstrating system level analysis  Network of relations  Mapping to Constraint Satisfaction Problem

4. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 4 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Qualitative Fault Modelling – Results and plans  Feasibility study finished (D3.1b)  Modelling a Car Alarm System  Abstraction by manual steps Spatial and temporal abstraction Syndrome level static modelling  Mapping to CSP using tools  Solution by CSP solver +model checker  Results and plans  Potentials of the approach were demonstrated Guiding heuristics for test generation (reducing search space) Supporting diagnostics  Application conditions were identified Target models: Networks of interconnected components  Automated abstraction: Elaboration of tool support would need more resources

5. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 5 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] WP3: Ontology-based Model Verification András Pataricza, Professor Budapest University of Technology and Economics

6. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 6 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Ontology Based Verification – Objectives  Verification of application specific models to have  well-defined,  consistent,  complete models,  which meet some modelling constraints. These application models are the inputs to test case generation.

7. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 7 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Ontology Based Verification – Progress  Deliverable 3.3a – Ontology based model verification ( M18 )  First version  Identification of modelling constraints  Theory of ontology based verification  Application of it in MOGENTES verification of the application model as a UML model verification of the application model as a domain model verification of instance models with respect to the application models  Verification of process models Done

8. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 8 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Examples of Constraints That are Checked  Class Diagram related  Consistency, coherence  State machine diagram exists for all active classes  Coverage of all defined input and other non-output signals by at least one transition trigger  State Machine related  Each state is targeted by at least one transition  State machines are deterministic  Behavior related  Sufficient method definition  Find unused methods  Application related  Existence of a marked up singleton class representing the system itself

9. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 9 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Ontology Based Verification – Implementation

10. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 10 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Ontology Based Verification – Framework Process Implementation Step 1: Transformation Step 2: Execution of verification

11. MOdel-based GENeration of Tests for Embedded Systems #216679 FP7-ICT-2007-1-3.3 Embedded Systems Design Slide 11 MOGENTES Review, Vienna, 11 March 2010 [ WP3 – Modelling and Testing Theory ] Ontology Based Verification – Planning  Deliverable 3.3b – Ontology based model verification ( M30 )  Improved version of D3.3a  Identification of new modelling constraints based on modelling experiences  Verification of final Mogentes demonstrator models  Improvement of the ontology-based model verification tool