1. Registers and Counters
Chapter 12
Registers and Counters
Ilsub Chung
( )

2. Analysis and Design of Combinational Logic
Outline
Last Time
Flip-flops
Flip-flop Timing Specifications
Simple Counters

3. General Simple Counters
Digital counter consists of a collection of flip-flops
Change states in prescribed sequence
Flip-flops are commonly used to design counters
Most straightforward counter is ripple divider
Use T FF or Toggle FF
J-K flip-flop can be converted to a T or toggle flip-flop
By connecting together J and K inputs

4. Divide by 2 Counter Simple Counters
Clock input can be used as a data input
Divide by 2 circuit divides input CK by 2
J, K inputs are connected together and pulled up to Vcc
Force excitation inputs “high”
Causing FF to toggle on every CK
If negative edge pulse is used

5. Divide by 4 Counters Simple Counters
Divide by 4 Counter requires 2 FFs
Divide by 4 counter divides the input CK frequency by “4”
Both J-K FFs are connected
To form toggle FF with Q output of 1st FF
Providing the input to the second
2nd FF divides the Q output from 1st FF by 2
Thereby dividing the input frequency “4”

6. Divide 8 Counters Simple Counters Requires 3 FFs
Each FF is connected as a toggle flip-flop
All J-K FFs are connected to toggle with Q output of 1st FF
Providing the input to 2nd FF, Q output to 3rd input
Asynchronous counter
Modulo-n counters
N states : terminal count
Modulo-8 counter has 8 states

7. Johnson Counter Simple Counters
Connecting output of one FF to input of another FF FF
Offset by a CK pulse from preceding FF output
Produce a series of outputs from each FF
Offset by one CK pulse from preceding FF output
Synchronous operation
CK pulse cause FF action at the same CK time
Q’D is fed back to DA

8. Johnson Counter Simple Counters Initially reset all FF
Negative edge of 1st set FF A : QA is “1”
The states of other FFs do not change
No input change
2nd CK pulse set FF B, 3rd set FF C, etc.
4th CH set FF D : QD is “1”
Q’D is “0”
Changing QA
Johnson Counter can be used to produce time delay

9. Ring Counter Simple Counters
Ring counter produces a continuous pattern from FF outputs
Ability to load particular state
Synchronous operation
Initialized using “PRE and RESET
Active low input : FF3, FF5, FF6, FF8
Others are reset
Data are shifted from one FF to next on
Negative edge of CK pulse

10. Ring Counter Simple Counters Assume 10001100 is preloaded
1st negative CK pulse : Q1 goes to “0”
Q2 change its state also : “0”->”1”
Generate a repeating n-bit pattern
LSB output is connected to MSB input

11. MSI Integrated Circuits
Flip-Flops, Simple Counters, and Resisters
MSI Integrated Circuits
Various counter is possible
Simple ripple binary counters
Synchronous up-down decade counters

12. MSI Asynchronous Counters
MSI Integrated Circuit Counters
MSI Asynchronous Counters
SN74176 is a TTL MSI decade or BCD counter
2 Clock inputs
Asynchronous
1st CK input is present only for 1st FF
FF can be used as a high speed prescaler
Divide by 2
Q output of FF A is not connected to others
Allow user to connect it to 2nd CK input
Or use the single FF separately from remaining 3 FFs
FF B and D are triggered by the CK 2 inputs
FF C is triggered by QB

13. MSI Asynchronous Counters

14. MSI Integrated Circuit Counters
Configurable Counter

15. MSI Integrated Circuit Counters
Binary Counter

16. MSI Synchronous Counter
MSI Integrated Circuit Counters
MSI Synchronous Counter
Synchronous counters have all CK inputs to FF connected together
State changes occur simultaneously
Synchronous operation
Initialized using “PRE and RESET
Active low input : FF3, FF5, FF6, FF8
Others are reset
Data are shifted from one FF to next on
Negative edge of CK pulse

17. MSI Synchronous Counter
MSI Integrated Circuit Counters
MSI Synchronous Counter
To provide even longer count sequences : Cascade
ENP, ENT, and RCO lines
RCO is an output signal asserted when terminal count is reached
It is used to link a lower order decade counter to next higher order
ENT and ENP are input enable signals : Control counting counter
Connecting RCO-ENT : cascading
Common CK is presented to all of ICs in parallel
Ripple carry from one decade to another is provided by RCO-ENT
ENT signal is used to control the entire counter

18. MSI Synchronous Counter
MSI Integrated Circuit Counters
MSI Synchronous Counter

19. Sequential Circuit Models
MSI Integrated Circuit Counters
Sequential Circuit Models

20. Flip-Flops, Simple Counters, and Registers
Chapter 5
Flip-Flops, Simple Counters, and Registers
Ilsub Chung
( )

21. Outline
Last Time
Simple Counters
Register

22. General Simple Counters
Digital counter consists of a collection of flip-flops
Change states in prescribed sequence
Flip-flops are commonly used to design counters
Most straightforward counter is ripple divider
Use T FF or Toggle FF
J-K flip-flop can be converted to a T or toggle flip-flop
By connecting together J and K inputs

23. Divide by 2 Counter Simple Counters
Clock input can be used as a data input
Divide by 2 circuit divides input CK by 2
J, K inputs are connected together and pulled up to Vcc
Force excitation inputs “high”
Causing FF to toggle on every CK
If negative edge pulse is used

24. Divide by 4 Counters Simple Counters
Divide by 4 Counter requires 2 FFs
Divide by 4 counter divides the input CK frequency by “4”
Both J-K FFs are connected
To form toggle FF with Q output of 1st FF
Providing the input to the second
2nd FF divides the Q output from 1st FF by 2
Thereby dividing the input frequency “4”

25. Divide 8 Counters Simple Counters Requires 3 FFs
Each FF is connected as a toggle flip-flop
All J-K FFs are connected to toggle with Q output of 1st FF
Providing the input to 2nd FF, Q output to 3rd input
Asynchronous counter
Modulo-n counters
N states : terminal count
Modulo-8 counter has 8 states

26. Johnson Counter Simple Counters
Connecting output of one FF to input of another FF
Offset by a CK pulse from preceding FF output
Produce a series of outputs from each FF
Offset by one CK pulse from preceding FF output
Synchronous operation
CK pulse cause FF action at the same CK time
Q’D is fed back to DA

27. Johnson Counter Simple Counters Initially reset all FF
Negative edge of 1st set FF A : QA is “1”
The states of other FFs do not change
No input change
2nd CK pulse set FF B, 3rd set FF C, etc.
4th CH set FF D : QD is “1”
Q’D is “0”
Changing QA
Johnson Counter can be used to produce time delay

28. Ring Counter Simple Counters
Ring counter produces a continuous pattern from FF outputs
Ability to load particular state
Synchronous operation
Initialized using “PRE and RESET
Active low input : FF3, FF5, FF6, FF8
Others are reset
Data are shifted from one FF to next on
Negative edge of CK pulse

29. Ring Counter Simple Counters Assume 10001100 is preloaded
1st negative CK pulse : Q1 goes to “0”
Q2 change its state also : “0”->”1”
Generate a repeating n-bit pattern
LSB output is connected to MSB input

30. MSI Integrated Circuits
Flip-Flops, Simple Counters, and Resisters
MSI Integrated Circuits
Various counter is possible
Simple ripple binary counters
Synchronous up-down decade counters

31. MSI Asynchronous Counters
MSI Integrated Circuit Counters
MSI Asynchronous Counters
SN is a TTL MSI decade or BCD counter
2 Clock inputs
Asynchronous
1st CK input is present only for 1st FF
FF can be used as a high speed prescaler
Divide by 2
Q output of FF A is not connected to others
Allow user to connect it to 2nd CK input
Or use the single FF separately from remaining 3 FFs
FF B and D are triggered by the CK 2 inputs
FF C is triggered by QB

32. MSI Asynchronous Counters