1. Advanced Implantation Detector Array (AIDA): Update & Issues Tom Davinson School of Physics The University of Edinburgh presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh – Liverpool – STFC DL & RAL)

2. DESPEC: Implantation DSSD Concept SuperFRS, Low Energy Branch (LEB) Exotic nuclei – energies ~ 50 – 200MeV/u Implanted into multi-plane, highly segmented DSSD array Implant – decay correlations Multi-GeV DSSD implantation events Observe subsequent p, 2p, , , ,  p,  n … decays Measure half lives, branching ratios, decay energies … Tag interesting events for gamma and neutron detector arrays

3. Implantation DSSD Configurations Two configurations proposed: a)8cm x 24cm “cocktail” mode many isotopes measured simultaneously b) 8cm x 8cm high efficiency mode concentrate on particular isotope(s)

4. AIDA: DSSD Array Design 8cm x 8cm DSSDs common wafer design for 8cm x 24cm and 8cm x 8cm configurations 8cm x 24cm 3 adjacent wafers – horizontal strips series bonded 128 p+n junction strips, 128 n+n ohmic strips per wafer strip pitch 625  m wafer thickness 1mm  E, Veto and up to 6 intermediate planes 4096 channels (8cm x 24cm) overall package sizes (silicon, PCB, connectors, enclosure … ) ~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm courtesy B.Rubio

5. ASIC Design Requirements Selectable gain20100020000MeV FSR Low noise12 60050000keV FWHM energy measurement of implantation and decay events Selectable threshold< 0.25 – 10% FSR observe and measure low energy  detection efficiency Integral non-linearity 95% FSR spectrum analysis, calibration, threshold determination Autonomous overload detection & recovery ~  s observe and measure fast implantation – decay correlations Nominal signal processing time < 10  s observe and measure fast decay – decay correlations Receive (transmit) timestamp data correlate events with data from other detector systems Timing trigger for coincidences with other detector systems DAQ rate management, neutron ToF

6. Schematic of Prototype ASIC Functionality Note – prototype ASIC will also evaluate use of digital signal processing Potential advantages decay – decay correlations to ~ 200ns pulse shape analysis ballistic deficit correction

7. Design Study Conclusions 4’’ or 6” Si wafer technology? - integrated polysilicon bias resistors (15M  ) - separate coupling capacitors (require 22nF/200V+) Radiation damage mitigation measures essential - detector cooling required Noise specification (12keV FWHM) … “not unreasonable” Discriminator - low threshold ( 100nA - separate timing discriminator – higher threshold x1000 overload recovery ~  s achievable - depends on input pulse shape - optimisation requires more information

8. AIDA Design Concept Detail of DSSSD detector layers and detector enclosure Beam courtesy Dave Seddon & Rob Page, University of Liverpool

9. AIDA: Current Status Edinburgh – Liverpool – CCLRC DL – CCLRC RAL collaboration - 4 year grant period - DSSD design, prototype and production - ASIC design, prototype and production - Integrated Front End FEE PCB development and production - Systems integration - Software development Deliverable: fully operational DSSD array to DESPEC Proposal approved & fully funded - project commenced August 2006 Detailed specification published November 2007 Technical Specification release to project engineers January 2007 Detailed ASIC design & engineering underway

10. AIDA: Resources & Tasks Cost Total announced value proposal £1.96M Support Manpower CCLRC DLc. 4.2 SYFEE PCB Design DAQ h/w & s/w CCLRC RALc. 3.5 SYASIC Design & simulation ASIC Production Edinburgh/Liverpoolc. 4.5 SYDSSD Design & production FEE PCB production Mechanical housing/support Platform grant support CCLRC DL/Edinburgh/Liverpool

11. AIDA: Current Status DSSD request for tender Prototype ASIC design submission 2008/Q1 FEE design underway liquid cooling required (cf. AGATA digitiser module) Evaluating 10nF/100V capacitor arrays Analog Devices AD9252 14-bit/50MSPS ADC DSSD response high energy heavy-ions simulations Luigi Bardelli et al. Texas A&M (40MeV/u) November 2008 GSI (100MeV/u) March 2009

12. Outstanding Issues: approaching the Rubicon Package size 10cm x 26cm x 4cm (10cm x 10cm x 4cm) Mechanical design concepts 10cm x 26cmAIDA/ToF/Ge 10cm x 26cmAIDA/4  Neutron Detector 10cm x 10cmAIDA/TAS … others? Review ASIC Project Specification DESPEC project requirements satisfied?

13. AIDA/ToF/Ge

14. AIDA/4  Neutron (NERO)

15. AIDA/TAS

16. AIDA Project Information Project web site http://www.ph.ed.ac.uk/~td/AIDA/welcome.html Design Documents http://www.ph.ed.ac.uk/~td/AIDA/Design/design.html Project Technical Specification ASIC Project Specification v1.3 FEE Specification v0.5 The University of Edinburgh (lead RO) Phil Woods et al. The University of Liverpool Rob Page et al. STFC DL & RAL John Simpson et al. Project Manager: Tom Davinson

17. Acknowledgements This presentation includes material from other people Thanks to: Ian Lazarus & Patrick Coleman-Smith (STFC DL) Steve Thomas (STFC RAL) Dave Seddon & Rob Page (University of Liverpool) Berta Rubio (IFIC, CSIC University of Valencia)

19. Implantation – Decay Correlation DSSD strips identify where (x,y) and when (t 0 ) ions implanted Correlate with upstream detectors to identify implanted ion type Correlate with subsequent decay(s) at same position (x,y) at times t 1 (,t 2, …) Observation of a series of correlations enables determination of energy distribution and half-life of radioactive decay Require average time between implants at position (x,y) >> decay half-life depends on DSSD segmentation and implantation rate/profile Implantation profile  x ~  y ~ 2cm,  z ~ 1mm Implantation rate (8cm x 24cm) ~ 10kHz, ~ kHz per isotope (say) Longest half life to be observed ~ seconds Implies quasi-pixel dimensions ~ 0.5mm x 0.5mm

20. AIDA: General Arrangement

21. Representative ASIC Noise Analysis Minimise ballistic deficit shaping time >10x t r operate with  ~  s noise dominated by leakage current for I D > 10 nA Note – amongst other assumptions, we assume detector cooling

22. AIDA: Workplan

25. Diagram (above) of the FEE boards as they would fit in the vertical plane. The grey rectangles are heat conductive foam pads which conform to the component outlines and conduct the heat to the water cooled metalwork. The green is pcb, the orange is a Samtec 80 pin connector with a 2.3mm height and the dark brown is the ASIC. The connections to the detector will be on the mezzanine boards to the left and to the acquisition network computers and BUTIS on the right. These are not shown. Diagram ( alongside) shows the layout of a sub-board.