1. GCT Source Card Status 11.5.06 John Jones Imperial College London john.jones@imperial.ac.uk

2. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR2 10.5.06 Role of the Source Card Capture data from RCT Relay data from RCT via optical links to GCT Leaf Card with minimal latency Provide test pattern transmission to Leaf Card for run-time debugging RCT Crate Source Card Crate Leaf Card RCT Crate Leaf Card RCT Crate

3. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR3 10.5.06 Design Summary 6U VME Card USB 2.0 Interface 2xVHDCI SCSI RCT Inputs 4xSFP optical outputs TTC input QPLL, TTCrx Spartan-3 1M FPGA Digital/Analogue supplies Limited spare I/O for debug Front panel JTAG Limited remote update ability On-board LVDS test clock 6 spare clock outputs

4. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR4 10.5.06 Source Card RCT Emulator Card Developed to drive RCT inputs of source card

5. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR5 10.5.06 Source Card Status Components ordered (awaiting lead time estimate) PCBs soon ready for manufacture (ahead of components) Board should be available in 4-6 weeks (depends on component lead time) Firmware test-benched & synthesised (see later) Software under development (see J. Brooke’s talk)

6. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR6 10.5.06 Registered Initial mode of operation Easier, but higher latency – can be tuned and not as bad as one might think… 6+2+(14+)+2+(21.25 23.75) = 45.25 47.75ns Source Card Source Card Latency I RCTVHDCI BUFFER DECL->TTL SERDES Leaf ~100ns 3m, ~15ns 6ns 2ns 14+ns 2ns 21.25-23.75ns Extra register with phase- shifted clock FPGA

7. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR7 10.5.06 Unregistered Tricky, not initial mode of operation as skew in FPGA difficult to control Phase of SERDES clock controlled via CLKDES on TTCrx 6+2+10+2+(21.25 23.75) = 41.25 43.75ns Doubtful whether this will be worth the effort… Source Card Source Card Latency II RCTVHDCI BUFFER DECL->TTL FPGA SERDES Leaf ~100ns 3m, ~15ns 6ns 2ns 10ns 2ns 21.25-23.75ns

8. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR8 10.5.06 Source Card Firmware - Architecture USB Wishbone Transcoder Data MUX LED Encoder SERDES Clock Local Clock Transmitter FSM Counter LFSR A-5 Wishbone Bridge RCT Data EMU/JET Switch Bit Mask Data Capture SERDES CRC-16 Transmitter Control TTC I 2 CTemp. I 2 C TTC Clock TTC Interface System Interface RAM

9. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR9 10.5.06 Source Card Firmware - Status USB Wishbone Transcoder Data MUX LED Encoder Simulated Transmitter FSM Counter LFSR A-5 Wishbone Bridge RCT Data Data Capture SERDES CRC-16 Transmitter Control TTC I 2 CTemp. I 2 C Real-World Tested TTC Interface System Interface RAM Bit Mask EMU/JET Switch

10. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR10 10.5.06 Drive RCT inputs using Source Card Test Card via IDAQ Send via IDAQ USB, readout via Source Card USB Synchronising clock provided locally / via TTC Verify A-5, PRBS, counter Source Card Testing Plan I SCTC Source Card USB RCT IN IDAQ OPTO 1 OPTO 2 OPTO 4 OPTO 3 FPGA TTC CLKBUF

11. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR11 10.5.06 Demonstrate fake data capture at leaf Synchronise via TTC / local Source Card Testing Plan II Source Card USB RCT IN OPTO 1 OPTO 2 OPTO 4 OPTO 3 FPGA TTC LEAF SCTC IDAQ CLKBUF

12. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR12 10.5.06 Demonstrate RCT data capture in Source Card Synchronise via TTC Source Card Testing Plan III RCT Source Card USB RCT IN FPGA TTC

13. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR13 10.5.06 Demonstrate RCT data capture at Leaf Card Synchronise via TTC / local Source Card Testing Plan IV Source Card USB RCT IN OPTO 1 OPTO 2 OPTO 4 OPTO 3 FPGA TTC LEAF RCT CLKBUF

14. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR14 10.5.06 Proposed Source Card Crate Layout 4 Source Card crates serve 18 RCT crates

15. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR15 10.5.06 USB 2.0 Hardware Interface VMEbus SBC running Linux 3 front panel USB port 10/100Base TX Ethernet Internal Hard drive Pentium Processor 7-port USB hub 7-port USB hub Source Card To monitor a 12-card crate To monitor a 15-card crate 7-port USB hub 7-port USB hub Source Card

16. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR16 10.5.06 USB 2.0 Hub Board Artwork for hub mounting card has been completed and prototype is in production at Imperial

17. John Jones (IC - john.jones@imperial.ac.uk), GCT ESR17 10.5.06 Summary Submission of Source Card PCB slightly delayed… …but other associated components on track… Plan to complete interfaces (software/PC) before PCB return in mid-late June