1. © 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow

2. Wrap up: DSP Design Flow - 7 - 3 © 2003 Xilinx, Inc. All Rights Reserved Module 1 Describe why parallelism enables high performance Describe the Virtex™-II, Virtex-II Pro™, and Spartan™-3 family architectural resources that are useful for DSP functions How do Xilinx FPGAs lend to an optimum implementation of DSP functions?

3. Wrap up: DSP Design Flow - 7 - 4 © 2003 Xilinx, Inc. All Rights Reserved Module 1: Answers Describe why FPGA enables high performance –Flexibility of parallel execution of basic functions due to uniform architectural resources –Tailoring to desired bit-width –Ease of applying varying sample rates Describe the Virtex™-II, Virtex-II Pro™, and Spartan™-3 family architectural resources that are useful for DSP functions –SRL16E –Distributed RAM –Block RAM –Embedded multipliers –Abundant logic and register resources

4. Wrap up: DSP Design Flow - 7 - 5 © 2003 Xilinx, Inc. All Rights Reserved Module 1: Answers How do Xilinx FPGAs lend to an optimum implementation of DSP functions? –SRL16E: storing samples when number of taps is small; implementing serial distributed arithmetic technique-based filters –Distributed RAM: To hold samples and coefficients in case of small filters; works efficiently when number of taps is in multiples of 16 –Block RAM: Suitable for storing large number of coefficients and samples –Embedded multipliers: suitable for applications that use multipliers with adjacent block RAM

5. Wrap up: DSP Design Flow - 7 - 6 © 2003 Xilinx, Inc. All Rights Reserved Module 2 Describe the advantages and disadvantages of three different design flows Describe the System Generator and the tools it interfaces with Describe steps involved in the Hardware in the Loop verification

6. Wrap up: DSP Design Flow - 7 - 7 © 2003 Xilinx, Inc. All Rights Reserved Module 2: Answers Describe the advantages and disadvantages of three different design flows –VHDL based designs Advantages: Portability, complete control of the design implementation and tradeoffs, easier to debug Disadvantages: Time-consuming, need to be familiar with the algorithm and how to write it, must be conversant with the synthesis tools to obtain optimized design –CORE Generator based designs Advantages: Quick access to existing functions, IP is optimized for the specified architecture Disadvantages: May not have exact functionality –System Generator based design Advantages: High productivity, ability to simulate at a system level, very attractive for FPGA novices, hardware in the loop simulation improves productivity and accelerates verification Disadvantages: Doesn’t always give the best result from an area usage point of view, not well suited to multiple clock designs, no bi-directional bus supported

7. Wrap up: DSP Design Flow - 7 - 8 © 2003 Xilinx, Inc. All Rights Reserved Module 2: Answers Describe the System Generator and the tools it interfaces with –The System Generator is a toolbox running under the Simulink environment that provides an integrated design flow by leveraging existing technologies such as HDL synthesis, IP Core libraries, and FPGA implementation tools. It provides a simple push-button flow for HDL Co-simulation and Hardware in the Loop acceleration verification capabilities Describe the Hardware in the Loop and the steps involved in the verification –Hardware in the Loop is a Simulink hardware accelerator, which enables design verification in hardware. It is a Simulink-to-bitstream-to-Simulink push button flow to simulate HDL and EDIF-based design –Three simple steps Insert a compilation block from the vendor library into the user model Compile (Generate) the design for the co-simulation Copy a co-simulation run-time block into the user model

8. Wrap up: DSP Design Flow - 7 - 9 © 2003 Xilinx, Inc. All Rights Reserved Module 3 State some of the digital filter blocks supported in System Generator Describe the factors that will determine the digital filter implementation Describe the integration of FDATool block in System Generator

9. Wrap up: DSP Design Flow - 7 - 10 © 2003 Xilinx, Inc. All Rights Reserved Module 3: Answers State some of the digital filter blocks supported in System Generator –FIR block –CIC block Describe the factors that will determine the digital filter implementation –Sample rate –Sample width –Coefficients profile –Clock rate Describe the integration of FDATool block in System Generator –The Xilinx FDATool (Filter Design and Analysis Tool) block provides an interface to the FDATool software available as part of the MATLAB Signal Processing Toolbox. It provides a powerful means for defining digital filters with a graphical user interface and storing it as part of a System Generator model

10. Wrap up: DSP Design Flow - 7 - 11 © 2003 Xilinx, Inc. All Rights Reserved Module 5 What is quantization? Why does it occur? State the two options available to handle it? What is an overflow? Why does it occur? State the three options available to handle it? Why do we need bit picking? State the four blocks available for this purpose?

11. Wrap up: DSP Design Flow - 7 - 12 © 2003 Xilinx, Inc. All Rights Reserved Module 4: Answers What is quantization? Why does it occur? State the two options available to handle it? –Quantization is a process of handling higher-precision number representation with a lower-precision number representation –In Simulink the numbers are represented in double-precision whereas in Xilinx Blockset, the numbers are represented in fixed-point –Truncate and Rounding are the two options available to handle it What is an overflow? Why does it occur? State the three options available to handle it? –An overflow occurs when a large number is represented in a smaller range representation –In Simulink, the numbers are represented in double-precision whereas in Xilinx Blockset, the numbers are represented in fixed-point –Saturate, Wrap the value, and Flag an error are the three options available

12. Wrap up: DSP Design Flow - 7 - 13 © 2003 Xilinx, Inc. All Rights Reserved Module 4: Answers Why do we need bit picking? State the four blocks available for this purpose? –There may be a need to Combine two data buses together to form a new bus Force a conversion of data type including the number of bits and binary bits Reinterpret unsigned data as signed, or the converse Extract certain bits of data, especially when there is bit growth –The four blocks available are Concat Convert Reinterpret Slice

13. Wrap up: DSP Design Flow - 7 - 14 © 2003 Xilinx, Inc. All Rights Reserved Module 5 Describe the control mechanisms available in System Generator State the available blocks in System Generator to control data movement

14. Wrap up: DSP Design Flow - 7 - 15 © 2003 Xilinx, Inc. All Rights Reserved Module 5: Answers Describe the control mechanisms available in System Generator –There are two mechanisms available in System Generator to control the data flow Enable ports Reset ports –Enable port, if available, is connected to a signal that is asserted at a multiple of the block 's sample rate and must be of Boolean type –Reset port, if available, is connected to a signal that is when asserted places the block in its initial state. The signal must be of Boolean type State the available blocks in System Generator to control data movement –MCode block –Expression block –Mealy State Machine block –Moore State Machine block

15. Wrap up: DSP Design Flow - 7 - 16 © 2003 Xilinx, Inc. All Rights Reserved Module 6 Define multi-channel and multi-rate systems State sample rate changing blocks Describe Simulink propagation rules

16. Wrap up: DSP Design Flow - 7 - 17 © 2003 Xilinx, Inc. All Rights Reserved Module 6: Answers Define multi-channel and multi-rate systems –A system is said to have multiple channels when same datapath processing is taking place in parallel –Multi-rate systems are those that have varying sampling rates needs State sample rate changing blocks –Up Sample –Down Sample –Parallel to Serial –Serial to Parallel

17. Wrap up: DSP Design Flow - 7 - 18 © 2003 Xilinx, Inc. All Rights Reserved Module 6: Answers Describe Simulink propagation rules –All blocks inherit their input sample rate –SysGen idiom: “explicit inherited” sample period tells Simulink to inherit first encountered sample time –Feedback loops cause problems for Simulink’s propagation algorithms Must set at least one explicit sample time in every feedback loop