1. Tezzaron Semiconductor FaStack Technology A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results

2. Tezzaron Semiconductor 3D Stacking Approaches Irvine Sensors : Stacked Flash Amkor : 4S CSP (MCP) Chip Level Density gain : “Yes” Cost impact: “Expensive” Speed gain: “Zero or Negative” Reliability: “No” Multi-Func: “Limited” Transistor Level : “Limited” only for PROM : “Expensive” due to low yield : “Extremely slow” : “No” Wafer Level Matrix: Vertical TFT Competitors : Conceptual Infineon/IBM RPI Ziptronix ZyCube TruSi Xan3D/Vertical Circuit/Tessera Tezzaron: 3 wafer stack : “Yes” : “Cost effective” : “Extremely fast” : “yes” Tezzaron: Actual

3. Tezzaron Semiconductor Wafer Level Stacking Approaches Infineon/IBM Impediments: Sliced wafer handling Alignment budget Uniform bonding Film stress during deep via fills Wafer warp Heat dissipation RPI/ Ziptronix/ ZyCube Impediments: Large alignment errors Strength/uniform bonding, voids Peeling propensity during thinning Film stress during deep via fills Wafer warp Heat dissipation Tezzaron 3 wafer stack “All key elements; Alignment, Bonding (Uniformity & Strength), Low thermal budget ( <400C), Si thinning (Control & Uniformity), Limiting stacking yield losses, Facile heat dissipation of wafer level stacking have been simultaneously integrated to meet market demand for density, cost and speed” Ziptronix : Covalent bond (4-inch) IBM : SOI wafer thinning Backside of the stacked wafer Infineon : W deep viaRPI : Dielectric bonding ZyCube : Injection glue bonding Tezzaron : Copper bonding 3D Sensor

4. Tezzaron Semiconductor The Objective

5. Tezzaron Semiconductor “It is clearly seen in Figure 1, that without further reductions in interconnect delay, reducing gate dimensions much below 130nm do not result in corresponding chip improvements.” NSA Tech Trends Q3 2003

6. Tezzaron Semiconductor Denser!

7. Tezzaron Semiconductor Faster! Shorter Wires t d  0.35 x rcl 2 Propagation delay is proportional to: 1 # of layers

8. Tezzaron Semiconductor Global Interconnect “problem” Span of Control

9. Tezzaron Semiconductor Lower Power! Power avg = Capacitance tot x Voltage 2 x Frequency Therefore: Power avg  Capacitance tot Capacitance is mostly due to wires. Stacked wire length  1 # of layers Therefore: Power avg stacked  Power avg single layer # of layers

10. Tezzaron Semiconductor Lower Costs! Less processing per layer Better optimization per wafer Higher bit density (memories) Lower test cost (using Bi-STAR™) Higher yield (using Bi-STAR™)