1. ECE 353 Introduction to Microprocessor Systems
Week 9
Michael G. Morrow, P.E.

2. Topics Memory technologies
Organization and operation of typical SRAM, EPROM and flash memory devices
Memory subsystem design
Address decoder implementation
SRAM timing characteristics

3. Memory Terminology How could we classify memory devices?
Read-Only Memory (ROM)
In common usage, ROM is memory that is nonvolatile.
Random-Access Memory (RAM)
The time required to access any memory location is the same – i.e. it does not need to be accessed in a specific order.
In common usage, RAM is memory that can be read or written with equal ease.

4. Memory Technologies ROM (non-volatile) RAM (volatile)
Masked ROM
Field programmable
EPROM
OTP PROM (fuse or EPROM)
Electrically erasable
EEPROM (or E2PROM)
Flash memory
RAM (volatile)
SRAM
DRAM
Pseudo-SRAM
Emerging memory technologies

5. Memory Organization Logical organization Physical organization
Organization as seen looking at the device from the outside
Linear array of registers (memory locations)
Width – number of bits in each memory location
Depth – number of memory locations
Usually written as depth x width (i.e. 32k x 8)
Physical organization
Different physical organizations can be used to implement the same logical organization
Physical organization affects performance and cost

6. SRAM Interfaces RAM with 3 control inputs RAM with 2 control inputs
/CS, /OE, /WE
Read
Write
aka “Intel style”
RAM with 2 control inputs
E (CS), R/W (or /WE)
aka “Motorola style”

7. SRAM Organization Logical Organization Physical Organization NV-SRAM
Typically 1, 4 , 8 or 16 bit widths
Physical Organization
Rectangular bit array
Two-level decoding (row and column)
Characteristic delays and timing requirements are specified in memory devices datasheet (Example)
NV-SRAM
Uses an alternate power source to maintain SRAM when system power is off
Requires logic to switch power sources and prevent spurious writes during power-up/power-down

8. EPROM Electrically programmable, non-volatile
Requires UV light to erase
Quartz window in package
Floating polysilicon gate avalanche injection MOS transistor (FAMOS)
Operation
Programmer loads device out-of-circuit
OTP EPROMs eliminate quartz window
EEPROMs are electrically erasable
Byte-erasable / writeable
Low-density
JEDEC Packages

9. Flash Memory Actually Flash EEPROM, commonly just called flash memory
Characteristics
Technologies
Endurance
Blocking, programming and erasing
Applications
ROM replacement
GP NV-RAM
Solid-state disk (flash-disk) Example

10. Memory Subsystem Design
Memory banks
Increasing memory width
Increasing memory depth
Increasing memory width and depth
Address decoding
Exhaustive (full) vs. partial (reduced) decoding
Boundaries
If address is a 2n boundary, then what is the result of (address AND (2n-1))?
We normally decode memory devices to be aligned on boundaries at least as large as they are

11. Memory Architectures Wide (n-byte) buses Bus resizing
Addressing effects
Byte transfer support
Data lanes
Control signals
Bus resizing
Static
Configurable
Dynamic

12. Memory Subsystems Review
What is the purpose of an address decoder circuit, and where does its output usually get connected?
What is exhaustive decoding, and what effects does it have?
What is partial decoding, and what effects does it have?

13. SRAM Timing Characteristics
An SRAM device has key timing parameters specified for the read cycle.
tAA – address access time
tRDHA – data valid after address changes
tACS – chip select access time
tRHCS – data valid after chip select
tCHZ – time until device floats bus
tOE – output enable access time
tOHZ – time until device floats bus
tRC – read cycle time
The write cycle has a complementary set of specifications.

14. 7C1046 SRAM

15. 27C512 EPROM

16. HM624100HC SRAM

17. SRAM Timing Compatibility
In order to ensure that we will be able to reliably read and write the memory device, we need to ensure that the processor system bus interface is compatible with the memory device.
This is accomplished by analyzing the timing for all relevant parameters of both the processor and memory, and ensuring that the operations can be completed reliably.

18. Wrapping Up
Quiz #2 will be held Wednesday 11/5/2007 at 7:15-8:30pm in 2317EH
Covers educational objectives for modules 3 and 4 (weeks 5 through 8)
Single 3x5 card with original handwritten notes
No calculators
Instruction set references and any needed datasheets will be provided
Reading for next week
Supplement #3, review chapter 9 in text

21. JEDEC Standard Packages

22. Flash Blocks

23. Flash Memory Application: Disk-on-Key
Up to 64GB nonvolatile storage
And climbing
No battery or power supply
Specifications:
Data retention up to 10 years
Erase cycles: 1,000,000 times
Shock resistance: 1000 G (maximum)

24. RAM Read – 3 control signals

25. RAM Write – 3 control signals

26. Increasing Memory Depth

27. Increasing Memory Width

28. Increasing Memory Depth & Width