1. ECE555 Lecture 3 Nam Sung Kim University of Wisconsin – Madison
Dept. of Electrical & Computer Engineering

2. Implementation Strategy for digital ICs

3. Impact of Implementation Choices
Domain-specific processor
(e.g. DSP)
10-100
Embedded microprocessor
Energy Efficiency (in MOPS/mW)
1-10
Hardwired custom
Configurable/Parameterizable
0.1-1
Somewhat
flexible
Fully
flexible
Flexibility (or application scope)
None

4. Implementation Choices
Custom
Standard Cells
Compiled Cells Ma
cro Cells
Cell-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
Array-based
Semicustom
Digital Circuit Implementation Approaches

5. The Custom Approach
Intel 4004
Courtesy Intel

6. Transition to Automation and Regular Structures
Intel 4004 (‘71)
Intel 8080
Intel 8085
Intel 8286
Intel 8486
Courtesy Intel

7. Cell-based Design (or standard cells)
Routing channel
requirements are
reduced by presence
of more interconnect
layers

8. Standard Cell — Example
[Brodersen92]

9. Standard Cell – The New Generation
Cell-structure
hidden under interconnect layers

10. Standard Cell - Example
3-input NAND cell
(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

11. Automatic Cell Generations
Initial transistor
geometries
Placed transistors
Routed cell
Compacted cell
Finished
cell

12. A Historical Perspective: the PLAx 1 2
AND
plane
Product terms OR f

13. Inverting format (NOR-NOR) more effective
Two-Level Logic
Every logic function can be expressed in sum-of-products format (AND-OR)
minterm
Inverting format (NOR-NOR) more effective

14. PLA Schematics (Logic-level)

15. PLA Schematic (Transistor-level)

16. PLA Layout – Exploiting Regularity

17. Breathing Some New Life in PLAs
River PLAs
A cascade of multiple-output PLAs.
Adjacent PLAs are connected via river routing.
No placement and routing needed and output buffers and the input buffers of the next stage are shared.
Courtesy B. Brayton

18. Generated by hard-macro module generator
Macro Modules
25632 (or 8192 bit) SRAM
Generated by hard-macro module generator

19. “Soft” MacroModules

20. “Intellectual Property”
A Protocol Processor for Wireless

21. Semicustom Design Flow
HDL
Logic Synthesis
Floorplanning
Placement
Routing
Tape-out
Circuit Extraction
Pre-Layout Simulation
Post-Layout Simulation
Structural
Physical
Behavioral
Design Capture
Design Iteration

22. The “Design Closure” Problem
Iterative Removal of Timing Violations (white lines)

23. Integrating Synthesis w/ Physical Design
RTL
(Timing) Constraints
Physical Synthesis
Macromodules
Fixed netlists
Netlist with
Place-and-Route Info
Place-and-Route Optimization
Artwork

24. Late-Binding Implementation
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
Array-based

25. Gate Array — Sea-of-gates
Uncommited
Cell
Committed
Cell (4-input NOR)

26. Sea-of-gate Primitive Cells
Using oxide-isolation
Using gate-isolation

27. Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K
(0.6 mm CMOS)
Courtesy LSI Logic

28. The return of gate arrays?
Via programmable gate array (VPGA)
Via-programmable cross-point
metal-5
metal-6
programmable via
Exploits regularity of interconnect
[Pileggi02]

29. Prewired Arrays
Classification of prewired arrays (or field- programmable devices):
Based on Programming Technique
Fuse-based (program-once)
Non-volatile EPROM based
RAM based
Programmable Logic Style
Array-Based
Look-up Table
Programmable Interconnect Style
Channel-routing
Mesh networks

30. Open by default, closed by applying current pulse
Fuse-Based FPGA
antifuse polysilicon
ONO dielectric n +
antifuse diffusion 2 l
Open by default, closed by applying current pulse

31. Array-Based Programmable Logic5 4 O 3 2 1
Programmable
OR array O I 3 2 1
Fixed AND array
Programmable
OR array I 5 4 O 3 2 1
Fixed OR array
Programmable AND array
Programmable AND array O O O 3 2 1 O 3 O 2 O 1
PLA
PROM
PAL
Indicates programmable connection
Indicates fixed connection

32. Programming a PROM f 1 X 2 NA
: programmed node

33. i inputs, j minterms/macrocell, k macrocells
More Complex PAL
i inputs, j minterms/macrocell, k macrocells
From Smith97

34. Programmable Logic Block
2-input mux
Configuration A B S F= X 1 Y XY A F B 1 S

35. Logic Cell of Actel Fuse-Based FPGA

36. Look-up Table Based Logic Cell

37. Array-Based Programmable Wiring
Interconnect
Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks

38. Mesh-based Interconnect Network
Switch Box
Connect Box
Interconnect Point

39. Transistor Implementation of Mesh

40. RAM-based FPGA
Xilinx XC4000ex
Courtesy Xilinx

41. Design at a Crossroad: System-on-a-Chip
Embedded applications where cost, performance, and energy are the real issues!
DSP and control intensive
Mixed-mode
Combines programmable and application-specific modules
Software plays crucial role
RAM
500 k Gates FPGA
+ 1 Gbit DRAM
Preprocessing
Spectral
Multi-
Imager
system
+2 Gbit
DRAM
Recog-
nition mC
Analog
64 SIMD Processor
Image Conditioning
Array + SRAM
100 GOPS

42. Backup

43. Logic Transistor per Chip
Productivity
Logic Transistor per Chip
(M)
10,000,000
10,000
1,000
100 10 1
0.1
0.01
0.001
100,000,000
0.01
0.1 1 10
100
1,000
10,000
100,000
Logic Tr./Chip
1,000,000
10,000,000
Tr./Staff Month.
100,000
1,000,000
Complexity
58%/Yr. compounded
10,000
(K) Trans./Staff - Mo.
Productivity
100,000
Complexity growth rate
1,000
10,000 x x
100
1,000 x x
21%/Yr. compound x x x
Productivity growth rate x 10
100 1 10
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
Source: Sematech
Complexity outpaces design productivity

44. A Simple Processor
MEMORY
INPUT/OUTPUT
CONTROL
DATAPATH

45. A System-on-a-Chip: Example
Courtesy: Philips

46. Design Methodology
Design process traverses iteratively between three abstractions: behavior, structure, and geometry
More and more automation for each of these steps

47. PLA Layout – Exploiting RegularityV DD
GND f
And-Plane
Or-Plane