Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS

Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS
Welcome to Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS

Lattice Mach4000TM Lattice MachXOTM Lattice MachXPTM
Non-volatile Solutions Lattice Mach4000TM Lattice MachXOTM Lattice MachXPTM Jörg Siemers, TMM; Avnet-Memec

Mach4000 LatticeXP FPGA MachXO Crossover ispMACH CPLD I/O Registers
10000 LatticeXP FPGA MachXO Crossover 1000 ispMACH CPLD I/O 100 100 1000 10000 100000 Registers

ispMACH 4000 Family Overview
SuperFAST CPLD Family 400 MHz fMAX and 2.5ns tPD for high- system performance Low Static Power Full CMOS design with static power as low as 40W (Z-type) Low Dynamic Power 1.8V core for low dynamic power consumption Flexible Architecture Get designs to market fast Flexible Solution to 512 macrocells V, 2.5V or 1.8V supply - Commercial/Industrial/Automotive

ispMACH 4000 - Optimal CPLD Solutions
ORP Generic Logic Block I/O Block Global Routing Pool (GRP) BANK 0 BANK 1 400 Lattice Leadership 300 Lattice fMAX (MHz) 200 Competition A Competition B 100 256 512 768 1024 Density (Macrocells) SuperFAST Performance Flexible Architecture Mainstream CPLDs 40uW 1.8/2.5/3.3V Power Supply 1.8/2.5/3.3/5V I/O 32 to 512 Macrocells Commercial/Industrial/ Automotive Zero Power

ispMACH 4000 Family Supports 1.8, 2.5, or 3.3V Power Supply

ispMACH 4000 Automotive Applications 4000 Automotive Features
Operation –40OC to 125OC Highest Performance Design Flexibility Lowest Power Consumption 1.8, 2.5 and 3.3V I/O (with 5V Tolerance)

ispMACH 4000V Automotive Family
Macrocells fMAX(MHz) tPD (ns) tCO (ns) tS (ns) I/O Packages 32 168 7.5 4.5 30/32 44 TQFP 48 TQFP 64 168 7.5 4.5 30/ 32/64 44 TQFP 48 TQFP 100 TQFP 128 168 7.5 4.5 64/92/96 100 TQFP 128 TQFP 144 TQFP 256 168 7.5 4.5 64/96/128 100 TQFP 144 TQFP 176 TQFP

ispMACH 4000Z Automotive Family
Macrocells fMAX(MHz) tPD (ns) tCO (ns) tS (ns) I/O Packages 32 150 7.5 4.5 48 TQFP 64 150 7.5 4.5 32/64 48 TQFP 100 TQFP 128 150 7.5 4.5 64/92 100 TQFP 256 150 7.5 4.5 64/128 100 TQFP 176 TQFP

MachXO Crossover LatticeXP FPGA MachXO Crossover ispMACH CPLD I/O

MACHXO Bringing the Best Together FPGAs without Compromise FLASH
Reconfigurable MACHXO Non-Volatile SRAM FPGAs without Compromise

Fujitsu Technology Partnership
Proven 130nm and 90nm Industry Leading 130nm Flash 300mm Fab for Lower Costs 65nm Development Underway 130nm Logic 130nm Flash + Logic 1.2-volt core 1.2-volt core Geometry 90nm Logic Fujitsu & Lattice Bringing the Best Together 65nm Logic Time

MachXO Brings the Best Together
Attribute CPLD FPGA MachXO High Pin-to-Pin Speed  Fast Wide Logic High I/O to Logic Ratio Instant-On Register Intensive Distributed & Embedded Memory MachXO Brings Together CPLD and FPGA Attributes to Optimally Serve Traditional CPLD Applications

MachXO Key Features LUT Flexibility Non-volatility Embedded Memory
Non-Volatile Solution Single chip, instant-on, high security TransFR™ (TFR) Technology Simplifies in-field logic updates High Performance 3.5n pin-to-pin* LUT Based Flexibility 256 to 2,280 (LUT4s) 2K to 8K bits distributed memory I/O Intensive 78 to 271 I/O Flexible sysIOTM Buffers LVCMOS 33/25/18/15/12, LVDS**, PCI** sysMEMTM Block Memory ** Up to 28K bits of memory sysCLOCKTM PLLs** On Board Oscillator ~20MHz 1.2/1.8/2.5/3.3V Power Supply Options Low standby power 640 LUTs) LUT Flexibility Non-volatility Embedded Memory Performance

MachXO Block Diagram (1200 and 2280)
sysCLOCK PLLs Frequency Synthesis & Clock Alignment sysIO Buffers Support LVCMOS/LVTTL, LVDS and PCI Programmable Function Units (PFUs) (with RAM) sysMEM Block RAM 9kbit Dual Port Programmable Function Units (PFFs) (without RAM) Flexible Routing Optimized for Speed, Cost and Routability JTAG Port

MachXO Block Diagram (640 and 256)
Programmable Function Units (PFUs) (with RAM) Four banks of sysIO Buffers Support LVCMOS/LVTTL Programmable Function Units (PFFs) (without RAM) Flexible Routing Optimized for Speed, Cost and Routability JTAG Port MachXO 256 Two banks of sysIO Buffers Support LVCMOS/LVTTL

MachXO Configuration Options
On Chip FLASH Single Chip Solution Excellent Security FLASH MEMORY Control Logic Massively Parallel Wide Data Transfer ProvidesFast SRAM Configuration from FLASH “Instant-on” SRAM Config. Bits (Control Device Op.) Infinitely Reconfigure SRAM Through JTAG MachXO JTAG Port Reprogram FLASH Through JTAG Port Flash Configures Logic, Interconnect and Block RAM for User PROMs TransFR (TFR) Technology Simplifies In-Field Logic Updates

MachXO Simplifies In-Field Logic Updates
MachXO with TransFR (TFR) Technology Requirement Embedded Programming Minimum Downtime I/O States Preserved Device State Controlled  ispVM Embedded Background Program  Update SRAM <1mS  XFLASH TransFR ispVM Command Controls I/O & Device State  Transparent Field Reconfiguration (TransFR)

sysIO Interfaces sysIO Buffer Supports Multiple I/O Standards
LVTTL, LVCMOS 33/25/18/15/12 PCI* LVDS*, BLVDS**, LVPECL** Up to 8 I/O Banks For Flexibility in I/O Placement Hotsocketing Input leakage less than 1mA during power-up/power-down Power supplies can be sequenced in any order Programmable Slew Rate Programmable Drive Strength 4 to 20mA (3.3-volts) 4 to 20mA (2.5-volts) 4 to 16mA (1.8-volts) 4 to 8mA (1.5-volts) 2 to 6mA (1.2-volts) Programmable Pull-up, Pull-down, Bus-friendly Programmable Open Drain OE GOE Output data Output data TO DO PAD Fast output data signal Input data signal * MachXO 1200 and 2280 ** MachXO 1200 and 2280 with external resistors Programmable delay element

sysMEM Block RAM Provides 9,216 Bit Blocks 275MHz Operation
Efficient Implementation of Buffers Pseudo Single Port Dual Port FIFO Dual Port 8,192 X 1 8,192 X 1 8,192 X 1 8,192 X 1 4,096 X 2 4,096 X 2 4,096 X 2 4,096 X 2 2,048 X 4 2,048 X 4 2,048 X 4 2,048 X 4 1024 X 9 1024 X 9 1024 X 9 1024 X 9 512 X 18 512 X 18 512 X 18 512 X 18 256 X 36 256 X 36 256 X 36 RAM (Single Port) RAM (Dual Port) Configurable Width and Depth Single Port, Dual Port , Pseudo-dual Port, FIFO and ROM Modes FIFO Logic Included in EBR AD[12:0] DI[35:0] CLK RST WE CS[2:0] ADA[12:0] ADB[12:0] DIA[17:0] DIB[17:0] CLKA EBR EBR CLKB DO[35:0] RSTA RSTB WEA WEB CSA[2:0] CSB[2:0] DOA[17:0] D OB[17:0] ROM RAM (Pseudo Dual Port) FIFO WAD[12:0] AD[12:0] WD[35:0] RAD[12:0] RD[35:0] RCE RCLK EBR EBR CLK DO[35:0] WCLK CE WCE WE RST

(From post scalar divider, clock net or external pin)
sysCLOCK PLL Divider (1-12) PLL Divider (2,4, , 24) Phase & Duty Select Adjust Delay CLOCK IN (From pin or routing) CLOCK OUT LOCK Dynamic Delay Adjust 0.25ns Steps +/- 2ns Range Feedback (From post scalar divider, clock net or external pin) Divider (2,4, ,128) Frequency: 25MHz MHz VCO Frequency MHz Low Output Period Jitter: ~ +-120ps Programmable Phase /Duty Cycle (45 Degree Steps) Dynamic Delay Adjust Increments of 250ps with a total of 2ns lead or 2ns lag

Multiple Power Supply Options
1.2 to 3.3V for Chosen I/O Std. 1.2 to 3.3V for Chosen I/O Std. 1.2 Volts 3.3 Volts 3.3/2.5/1.8 Volts 3.3 Volts VCC VCCP VCCAUX VCCJ VCCIO VCC VCCP VCCAUX VCCJ VCCIO MachXO MachXO Internal logic operates at 1.2-volts Internal logic operates at 1.2-volts Lower Voltage (E) Version Upper Voltage (C) Version Use C Version to Access Latest Technology Without Adding New Power Supplies to Board Improve performance and power consumption Allows single supply operation from 3.3-volts Use E Version to Minimize Power Consumption 64% lower power than operation at 3.3-volts

Sleep Mode Reduces Power by Factor of 1000
SLEEPN Pin LatticeXO Device State Normal Sleep Mode Normal Typical 100nS Typical 1mS Mode Characteristic Normal Off Sleep SLEEPN Pin High X Low Static Icc Typical <100mA Typical <100uA Power Supplies Normal Range Logic Operation User Defined Non Operational I/O Operation Tri-State Note: Sleep Mode is only available on 1.8/2.5/3.3V “C” version

MachXO Benefits Self-Configuration in Under A Millisecond Single Chip
Instant-On ideal for system “heartbeat” control logic Supports configuration “scrubbing” for SEU control Supports rapid power cycling Single Chip Simplify design Reduced PCB footprint Save boot PROM costs High Security Security bits prevent readback No exposed power-up bitstream On-Chip Regulation Support legacy applications with latest technology Reduce costs Improve performance SRAM + FLASH TransFR (TFR) technology enables in field updates while system operates

Distributed RAM (KBits)
MachXO Family Members Device LCMXO 256 LCMXO 640 LCMXO 1200 LCMXO 2280 LUTs 256 640 1200 2280 Distributed RAM (KBits) 2 6.1 6.4 7.7 EBR SRAM (KBits) 9.2 27.6 # EBR SRAM Blocks (9Kb) 1 3 V Voltage 1.2/1.8/2.5/3.3V CC Number of PLLs 1 2 Max I/O 78 159 211 271 Packages: 100-TQ (14X14) 78 74 73 73 144-TQ (20X20) 113 113 113 csBGA 100 (8X8) 78 74 csBGA 132 (8X8) 101 101 101 fpBGA 256 (17X17) 159 211 211 fpBGA 324 (19X19) 271

LA-MachXO Family     LUTs sysMEM Blocks (9Kbits)
LAMXO 1200 LAMXO 2280 LAMXO 640 LAMXO 256 LUTs sysMEM Blocks (9Kbits) sysMEM EBR RAM (bits) Distributed RAM (k bits) sysCLOCK PLLs Global Clocks I/O Type Pb-Free Packages / IO 100 TQFP 144 TQFP 256 ftBGA 324 ftBGA Availability (E = 1.2V) (C = 3.3/2.5/1.8V) 256 2.0 4 LVCMOS 78  640 6.1 4 LVCMOS 74 113 159  1200 1 9216 6.4 2 4 LVCMOS PCI LVDS 73 113 211  No Plan1 2280 3 27648 7.7 2 4 LVCMOS PCI LVDS 73 113 211 271  No Plan1 1. Due to thermal consideration.

MachXO Summary MachXO Offers a Unique Combination of Flash and SRAM Technology to Deliver Non-Volatile, In-System Reconfigurable Logic MachXO Offers an Extremely Cost-Effective Alternative to High-End CPLDs and Low-End FPGAs with the Best Features of Both Applications for MachXO Span All Market Segments and Electronic Systems The Combination of LatticeEC/ECP/XP FPGAs and MachXO Gives Lattice the Broadest Portfolio of Low-Cost FPGAs Available

XP - non volatile FPGA Family

ispXP Bringing the Best Together FPGAs without Compromise FLASH
Reconfigurable ispXP Non-Volatile FPGAs without Compromise SRAM

Fujitsu Technology Partnership
Proven 130nm and 90nm Industry Leading 130nm Flash 300mm Fab for Lower Costs 65nm Development Underway 130nm Flash + Logic 130nm Logic 1.2-volt core 1.2-volt core Geometry 90nm Logic Fujitsu & Lattice Bringing the Best Together 65nm Logic Time

LatticeXP FPGA Key Features
Non-Volatile Reconfigurable Low Cost Solution Optimized architecture 0.13um Flash process Wide Density & I/O Selection 3k to 20k LUTs 62 to 340 I/Os Embedded & Distributed Memory 12kbits to 79kbits distributed in LUTs 54kbits to 414kbits embedded block High Performance (225MHz+) sysIO™ Interface Support LVCMOS, LVTTL, PCI, LVDS, SSTL, HSTL 333Mbps DDR Memory Interfaces sysCLOCK™ PLLs Two Core Power Supply Versions C = 1.8, 2.5, 3.3V Support E = 1.2V Support Non-Volatile Reconfigurable Flexible LUT-Based “No Compromise”

LatticeXP: Added Non-Volatility
ispXP FLASH Memory Instant-on, Secure and Single-chip sysMEMTM Block RAM 9kbit Dual Port sysCLOCKTM PLLs Frequency Synthesis & Clock Alignment Optimized sysIOTM Buffers Support Mainstream I/O: LVCMOS/LVTTL, LVDS, SSTL, HSTL, DDR Memory Interfaces JTAG Optimized Programmable Function Units (PFUs) 25% – Logic + RAM 75% – Logic Only Flexible Routing Optimized for Speed, Cost and Routability

LatticeXP Configuration Options
On Chip Non-Volatile Single Chip Solution Excellent Security FLASH MEMORY Control Logic Massively Parallel Data Transfer & Multiple Blocks Provide Secure and Fast SRAM Configuration “Instant-on” Parallel sysCONFIG™ to Configure SRAM or Program FLASH sysCONFIG Port SRAM Configuration Bits (Control Device Operation) Serial JTAG Port (IEEE 1532/1149.1) to Configure SRAM or Program FLASH JTAG Port Flash Configures Logic, Interconnect and Block RAM for User PROMs Background Flash Programming Support Upgrade system remotely Leave-Alone I/O Control I/O state while refreshing Control Logic FLASH MEMORY

Background Programming With LatticeXP
Background Programming of Flash Occurs While the Device is in Normal Operation Power Cycle or Apply a Refresh Command New/Updated Configuration Takes Control Program configuration #2 to FLASH via sysCONFIG or JTAG ports Logic operates based on SRAM configuration #1 FLASH (#1#2) FLASH Programming During Device Operation Logic operates based on SRAM configuration #2 FLASH (#2) Reload SRAM at Power-up or User Command

ispXP XP10 Programming Times SRAM Configuration FLASH Programming*
From FLASH 2ms Via sysCONFIG 11ms Via JTAG 100mS FLASH Programming* Via JTAG 2 Seconds Via sysCONFIG 2 Seconds Reconfigurable ispXP Non-Volatile * Programming time. Erase approximately 10 seconds

LatticeXP Wake-up Time
140 Altera 120 100 XP Advantage 80 Wake-up Time (mS) 60 Xilinx 40 20 Lattice EP1C12 XC3S1000 XP10 Fastest serial configuration LatticeXP Logic is Available 1mS After Power Good -- Supports “Instant-on” Application Requirements --

LatticeXP Integrates Multiple Components
Microprocessor Microprocessor CPLD Power up logic FPGA boot logic and bus decode Processor Address and Data Busses Processor Address and Data Busses FPGA Data Path function Voltage Regulator

LatticeXP FPGAs Secure Your Design
FPGA Security Important Due To Multiple Threats Reverse engineering Cloning Overbuilding Theft of service LatticeXP Security Scheme Allows Devices To Be Locked Secures SRAM and FLASH Erasing memory is only allowable operation 0.13um technology and 8 metal layers makes probing next to impossible Specify Secure Mode in ispLEVER or ispVM LatticeXP FPGAs Secure Your Design SRAM FPGAs Expose Your Intellectual Property At Power Up

Optimized PFU Logic Block
Carry Chain Optimized LatticeXP Devices Support 25% Distributed Memory Spartan3 50% Distributed Memory Incurs Unnecessary Die Cost Cyclone 0% Distributed Memory Impacts Logic Efficiency SLICE 3 LUT4 FF LUT4 FF SLICE 2 LUT4 FF Frequency of Usage (>250 Designs) LUT4 FF From To 10% LUTs Needed for Distributed Memory on Average Routing Routing SLICE 1 LUT4 FF 0% 50% LUT4 LUTs Used As Distributed Memory FF SLICE 0 Industry-standard 4-input LUT Structure Combine multiple LUTs for larger functions Carry Chain for arithmetic speed LUT4 FF LUT4 FF Logic Block (PFU) Optimized Architecture Delivers Uncommon Value Carry Chain

sysMEM Block RAM Provides 9,216 Bit Blocks 250MHz Operation
Single Port Dual Port Pseudo- 8,192 X 1 4,096 X 2 2,048 X 4 1,024 X 9 512 X 18 256 X 36 Provides 9,216 Bit Blocks 250MHz Operation Multiple Blocks per Device RAM (Single Port) RAM (Dual Port) AD[12:0] DI[35:0] CLK RST WE CS[2:0] ADA[12:0] ADB[12:0] DIA[17:0] DIB[17:0] CLKA EBR EBR CLKB DO[35:0] RSTA RSTB WEA Configurable Width and Depth Single Port, Dual Port , Pseudo-dual Port and ROM Modes Port Width Matching FIFO with surrounding logic WEB CSA[2:0] CSB[2:0] DOA[17:0] D OB[17:0] ROM RAM (Pseudo Dual Port) WAD[12:0] AD[12:0] WD[35:0] RAD[12:0] RD[35:0] RCE RCLK EBR CLK DO[35:0] WCLK EBR CE WCE WE RST

sysCLOCK PLL Frequency Range 25 to 375MHz Analog PLL Technology
Dynamic Delay Adjust LOCK Input Clock Divider (CLKI) PLL Post Scalar Divider (CLKOP) Phase & Duty Select CLOCK IN (From pin or routing) Delay CLOCK OUT Adjust CLOCK OUT 0.25ns Steps +/- 2ns Range Secondary Clock Divider (CLKOK) Feedback Divider (CLKFB) CLOCK OUT Feedback (From post scalar divider, clock net or external pin) Frequency Range 25 to 375MHz VCO range 420 to 750MHz Analog PLL Technology Low Output Period Jitter (+/- 125ps) Programmable Phase / Duty Cycle (45 degree steps) Programmable Dividers Internal and External Feedback

PIC 2-FF Output & Tri-state Structure Allows Easy DDR Implementation PIO A PIC Tri-state Register Block (2 Flip/flops) 5-Flip Flop Input Structure Allows Easy DDR Implementation (Including clock domain transfer) Output Register Block (2 Flip/flops) High performance sysIO Buffer (700 Mbps) Input Register Block (5 Flip/flops) Input Control Select 8 I/O Banks Allows Flexible I/O Implementation Dedicated Circuitry Simplifies DDR Memory Implementations (up to 333Mbps) DQS Delay and Transition Detect* PIO B (Detail Not Shown) * Selected blocks

I/O Banking Scheme Eight I/O Banks Per Device
Output Standard Support Dependent on VCCIO Referenced Inputs Dependent on VREF LVCMOS Inputs 12, 25 & 33 independent of VCCIO 15 & 18 dependent on VCCIO Multiple Compatible I/O Standards In A Bank GND GND CCIO0 REF1(0) REF2(0) CCIO1 REF1(1) REF2(1) Bank 0 Bank 1 V V CCIO7 CCIO2 V V REF1(7) Bank 7 REF1(2) V Bank 2 REF2(7) V REF2(2) GND GND V CCIO6 V CCIO3 V REF1(6) V Bank 6 REF1(3) V Bank 3 V REF2(6) REF2(3) GND GND Bank 5 Bank 4 CCIO5 REF1(5) REF2(5) GND CCIO4 REF1(4) REF2(4) GND V V V V V V

Clock Polarity Select* Exceptional DDR Performance
DDR Memory Interfaces DDR DRAM is the Low-Cost Memory of Choice >50% of 2004 Total DRAM Bits DDR to SDR De - mux Input Logic Block Half Clock Transfer Data Automatic Clock Transfer Circuitry Simplifies Design LatticeXP Pre-Engineered DDR Interfaces Precision DQS Delay Control (Temp. & Voltage-Compensated)  Dedicated DDR Registers (Fast Muxing/Demuxing) Automatic DQS to System Clock Domain Transfer Half Clock Transfer High-Performance 166MHz 333Mbps & Ensures Robust Operation DLL Calibrated Clock DQS to DQ Alignment DQS Clock Polarity Select* DDRCLKPOL DQS DQS Delay Block* * Selected Input Logic Blocks DDR Memory Interface Issues Bi-directional DQ & DQS Tight timing specifications Clock domain transfers Muxing/de-muxing data Exceptional DDR Performance

Multiple Power Supply Options
1.2 to 3.3V for Chosen I/O Std. 1.2 to 3.3V for Chosen I/O Std. 1.2 Volts 3.3 Volts 3.3/2.5/1.8 Volts 3.3 Volts VCC VCCP VCCAUX VCCJ VCCIO VCC VCCP VCCAUX VCCJ VCCIO Internal logic operates at 1.2-volts Internal logic operates at 1.2-volts Lower Voltage (E) Version Upper Voltage (C) Version Use C Version to Access Latest Technology Without Adding New Power Supplies to Board Improve performance and power consumption Allows single supply operation from 3.3-volts Use E Version to Minimize Power Consumption 64% lower power than operation at 3.3-volts

Sleep Mode Reduces Power by Factor of 1000
SLEEPN Pin Lattice XP Device State Normal Sleep Mode Normal Typical 100nS Typical 2mS Mode Characteristic Normal Off Sleep SLEEPN Pin High X Low Static Icc Typical <100mA Typical <100uA Power Supplies Normal Range Logic Operation User Defined Non Operational I/O Operation Tri-State Note: Sleep Mode is only available on 1.8/2.5/3.3V “C” version

Optimizing I/O Capability
80% Low Implementation Cost 70% High Implementation Cost 60% 50% 40% % Of High Volume Designs 30% 20% 10% 0% PCI LVTTL LVDS SSTL PCI-X HSTL HT/LDT LVCMOS LVPECL Percentage of XP I/O Supporting 100% 50% 100% 50% 0%* 100% 0% 100% 0% * Can be supported through emulation Optimized I/O Support Delivers Uncommon Value

LatticeXP Benefits Self-Configuration in Under A Millisecond
Ideal for system “heartbeat” control logic Supports configuration “scrubbing” for SEU control Supports rapid power cycling Single Chip Simplify design Reduced PCB footprint Save boot PROM costs High Security Security bits prevent readback No exposed power-up bitstream On-Chip Regulation Support legacy applications with latest technology Reduce costs Improve performance SRAM + FLASH Real time programming of device during operation

LatticeXP Family Device XP3 XP6 XP10 XP15 XP20 LUTs (K) 3.1 5.8 9.7
15.4 19.7 sysMEM Blocks 6 10 24 32 46 sysMEM (Kbits) 54 90 216 288 414 Distributed RAM (Kbits) 12 23 39 61 79 Voltage (V) 1.2/1.8/2.5/3.3V PLLs 2 4 Package I/O Combinations 100-pin TQFP (14x14mm) 62 144-pin TQFP (20x20mm) 100 208-pin PQFP (28x28mm) 136 142 256-ball fpBGA (17x17mm) 188 388-ball fpBGA (23x23mm) 244 268 484-ball fpBGA (23x23mm) 300 340

LatticeXP Value Proposition
Non-Volatile FPGA Single Chip High Security Instant-On Mainstream LUT-based Architecture Optimized Device Provides Low Cost Solution Manufacturable 130nm silicon process Best DDR Memory Support Easy design of 333Mbps interfaces Popular Packaging Options TQFP, PQFP, fpBGA RoHS / Lead-Free available Combines the Best of Non-Volatile & SRAM -- No Compromise FPGA!

Lattice Product Families
10000 LatticeSC System Chip LatticeECP/2/XP/ FPGA MachXO Crossover 1000 ispMACH CPLD I/O 100 100 1000 10000 100000 Density

LatticeSC Architecture
High Performance FPGA Fabric 4 to 32 SERDES (Up to 3.4Gbps) with Physical Coding Sublayer (PCS) 2Gbps PURESPEED I/O 15K to 115K LUT4s Up to 7.8 Mbits of Embedded Memory Blocks System-Level Features: Embedded System Bus / Dedicated Microprocessor Interface / SPI Flash Configuration MACO: Embedded Structured ASIC Blocks (LatticeSCM Devices) 8 Analog PLLs / 12 DLLs per Device 1.0V-1.2V Operating Voltage

Masked Array for Cost Optimization
Multiple 90nm Embedded 50K ASIC Blocks Ample FPGA-to-ASIC Signal Connectivity Ample ASIC-to-IO Connectivity High-speed Clock Connectivity

MACO: Standard Offerings
SERDES Quad SERDES Quad SERDES Quad SERDES Quad MACO EMB MACO A A EMB A B C C EMB C C F E B EMB B D PLC Array LatticeSCM25

LatticeSC(M) Family Device SC15 SC25 SC40 SC80 SC115 LUTs (K) 15.2
25.4 40.4 80.1 115.2 sysMEM Blocks (18Kb) 56 104 216 308 424 Embedded Memory (Mbits) 1.03 1.92 3.98 5.68 7.8 Distributed Memory (Mbits) 0.24 0.41 0.65 1.28 1.84 3.4Gbps SERDES 8 16 32 PLLs / DLLs 8 / 12 MACO Blocks* 4 6 10 12 Package I/O + SERDES Combinations (1mm Ball Pitch) 256-ball fpBGA (17x17) 139+4 900-ball fpBGA (31x31) 300+8 378+8 1020-ball ffBGA (33x33) 484+16 562+16 1152-ball fcBGA (35x35) 660+16 1704-ball fcBGA (42.5x42.5) 904+32 942+32 *Maximum Number of 50K Gate MACO Blocks. MACO Enabled Only on LatticeSCM Family

ispLEVER® Design Tools
OEM Tools integrated: Mentor Graphics Precision Synplicity Synplify Model Technologie ModelSim

ispLEVER® Design Tools
Unified GUI FPGA / FPSC / CPLD / SPLD PC, UNIX and LINUX Versions Integrated 3rd Party Synthesis and Simulation Tools Mentor Graphics Synplicity Free ispLEVER-starter will support every PLD device VHDL & Verilog Synthesis Schematic Module / IP manager ispTracy Logic Analyzer Simulator Floor Planner Pin Editor HDL Capture and Simulation Floorplanner Design Synthesis Mapping / Packing Design Database Logic Simulation and Timing Verification IP Manager Fitting / Place & Route Timing Analyzer Delay File “The Simple Machine for Complex Designs”

ispLEVER Configuration Options
Device Support Synthesis Support Simulation License Type ispLEVER - Stand-Alone Compiler All Lattice Programmable Logic: All Devices n/a Floating (UNIX/LINUX) Node Locked or Floating (PC) Includes Lattice device libraries to work with 3rd party EDA environments. (PC, UNIX) ispLEVER Base HDL All Devices Mentor Precision 2005b Synplicity Synplify 8.2h ModelSim 6.1a Lattice Functional Simulator Node Locked or Floating ispLEVER Starter New / Focus CPLD,MachXO, XPGA,GDX EC, ECP, XP3-XP6 Lattice Functional Simulator Node Locked: 6-Month Trial Intended for evaluation, and student users, ispLEVER Starter is a complete solution that can take your design from concept through device programming. (PC) Für SeminarTeilnehmer: 295€ Free SW

ispTRACY Debugging Environment

Evaluation Board Allows Many IPs to Be
Lattice IP Support PCI DDR I 1GB Ethernet MAC 10/100 Ethernet MAC QDR II SDRAM DMA I2C ….. and more see Evaluation Board Allows Many IPs to Be Checked Out In The Lab

JumpIn2Practice by eVision Systems
Get your ideas into the market, FAST - FPGA relevant Training content - All tutorials based on ispLEVER - Support you with BASIC and ADVANCED Course - Training Material that will become your day to day working book for the future YOUR SUCCESS IS OUR MISSION

JumpIn2Practice About eVision Systems
- independent EDA Company based in the Munich area - VHDL, Verilog and SystemC Tools - RFIC & MICROWAVE Design Tools - Technical Support Team - Training Services - Own HDL Design Experience

Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS

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