1. FX to FX2: A Comparison

2. Agenda Block diagram Evolution Hardware Firmware Wrap-up

3. Address (16) 8051 Core 24/48 MHz, 4 clocks/cycle CY Smart USB Engine 12 MHz XTAL I/O Ports (40) 4 KB / 8KB RAM Address (16) / Data Bus (8) X4 PLL I 2 C Compatible Four 64 bytes FIFO 8/16 bits Data(8) DMA Engine EZ-USBFX USB 1.1 XCVR D+ D- Uses Low-Cost Crystal High Performance Micro Using Standard Tools Memory Expansion or Data Buffer Ports Peripheral I/O Flexibility 1K Double-Buffer Isochronous Support "Soft Configuration” Easy Firmware Changes Enhanced USB Core Simplifies 8051 Code Master or Slave Operation Abundant I/O Including 2 UARTS Up to 48 MBytes/s Burst Rates GPIF General Programmable I/F to any ASIC/DSP or bus standards such as ATAPI, EPP, etc. 2 KB FIFO EZ-USB FX Block Diagram

4. EZ-USB FX2 Block Diagram 24 MHz XTAL Uses Low-Cost Crystal High Performance Micro Using standard tools with low power options Memory Expansion or Data Buffer Ports Peripheral I/O Flexibility "Soft Configuration” Easy Firmware Changes Enhanced USB Core Simplifies 8051 Code FIFO and Endpoint Memory (Master or Slave Operation) Abundant I/O Including 2 UARTS General Programmable Interface to any ASIC/DSP or bus standards such as ATAPI, EPP, etc. 8051 Core 12/24/48 MHz 4 clocks/cycle CY Smart USB Engine 8.5kB RAM Address (16) / Data Bus (8) X20 PLL 4kB FIFO EZ-USBFX2 USB 2.0 XCVR D+ D- GPIF ADDR (9) connect for full speed 1.5k Vcc I 2 C - Compatible Master /0.5 /1.0 /2.0 Additional I/Os (24) Data (8) Address (16) RDY (6) CTL (6) 8/16

5. EZ-USB FX2 Architectural Evolution Endpoint FIFOS Microprocessor Outside World (a) USB 1.1 Full Speed USB EZ-USB Endpoint FIFOS Microprocessor (c) USB 2.0--no time wasted transferring data between FIFOS Outside World USB RAM/FIFO access (36 kilobits) EZ-USB FX2 Endpoint FIFOS USB Microprocessor DMA Interface FIFO (b) USB 1.1 Full Speed Outside World RAM/FIFO access (24 kilobits)(2 kilobits) EZ-USB FX control

6. FX to FX2 Hardware - General Not pin compatible Internal resistor for DISCON pin Programmable WAKEUP with multiple sources Firmware SUSPEND Finally 115k and 230k baud internally with dedicated pins

7. FX vs. FX2 Hardware - General

9. FX to FX2 Hardware - Slave FIFOs Dedicated PKTEND pin More flags with more programmable flexibility Two address pins to select 1 of 4 FIFOs Same flexible programmable polarity for control pins

10. FX vs. FX2 Hardware - Slave FIFOs

11. FX to FX2 Hardware - GPIF GPIF sampling or sync clock either 30 or 48 MHz More address lines (9 vs. 6) GPIF signals are not muxed with GPIO signals

12. FX vs. FX2 Hardware - GPIF

13. FX vs. FX2 Hardware - I/F Clocking CLKOUT either 12, 24, or 48 MHz IFCLK can either be an input or an output

14. FX vs. FX2 Hardware - DK CPLD instead of 22V10 Same BRKPT LED plus four additional LED’s Switch selectable EEPROM size

15. FX to FX2 Firmware - USB Endpoint size and buffering is programmable Auto In/Out to take 8051 out of data path No separate ISO buffers Can turn off SOF generation Better setup data pointer No more busy bits From 16 endpoints to 7

16. FX vs. FX2 Firmware - USB

18. FX vs. FX2 Firmware - Slave FIFOs FIFOs individually selectable 8/16 wide FIFO empty + 1 and full -1 flags FIFO status registers in SFR space

19. FX vs. FX2 Firmware - GPIF New GPIF long transfer mode Can now check all flags in decision point GPIF trigger now in SFR space

20. FX to FX2 Firmware - 8051 Full 8k of internal memory for code & xdata More registers in SFR space I/O ports in SFR space only 8051 clock rate either 12, 24, or 48 MHz No more DMA Two autopointers

21. FX vs. FX2 Firmware - 8051