1. Chapter 4
Combinational Logic

2. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

3. 4.1 Introduction Logic circuits for digit systems maybe
combinational or sequential. 
A combinational circuit consists of logic gates whose outputs at any time are determend from only the presence combinations of inputs
A Sequential circuits contain memory elements with the logic gates the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs. (chapter 5)  2

4. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

5. Combinational circuits
A combinational circuits 
2 possible combinations of input values n 
Combinational circuits
n input m output
Combinatixnal
variables variables
xoxic Circuit
Specific functions 
Adders, subtractors, comparators, decoders, encoders, 
and multiplexers 4

6. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

7. 4.3 Analysis Procedure A combinational circuit
make sure that it is combinational not sequential 
No feedback path or memory elements. 
derive its Boolean functions (truth table) 
design verification 

8. Example: 6

9. F2= AB+AC+BC
T1= A+B+C
T2= ABC
T3= F2’. T1
F1= T3+T2
= F2’. T1 +ABC
= (AB+AC+BC)’.(A+B+C) +ABC
= (A’+B’)(A’+C’)(B’+C’).(A+B+C) +ABC
= (A’B’+A’B’C’+B’C’+A’C’). (A+B+C) +ABC
= AB’C’+A’B’C+A’B’C+ABC

10. The truth table  8

11. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

12. 4.4 Design Procedure The design procedure of combinational circuits
From the scpecification of the circuit determine the required number of inputs and outputs. 
For each input and output variables assign a symbol 
Derive the truth table  
Derive the simplified Boolan functions for each output as a function of the input variables 
Draw the logic diagram and verify the correctness of the design 9

13. Example: code conversion
BCD to excess-3 code 11

14. The maps 12

15. The simplified functions
z = D' 
y = CD +C'D‘
x = B'C + B‘D+BC'D'
w = A+BC+BD
Another i
mplementation  
z = D' 
y = CD +C'D' = CD + (C+D)'
x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)'
w = A+B(C+D) 13

16. The logic diagram  14

17. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

18. Half adder 4-5 Binary Adder-Subtractor
0 + 0 = 0 ; = 1 ; = 1 ; = 10 
two input variables: x, y 
two output variables: C (carry), S (sum) 
truth table 
S = x'y+xy‚ S=xÅy
C = xy 15

19. 17

20. Full-Adder Z X 1 + Y + 0 + 1 C S 0 1 1 0 Z 1 X + Y + 0 + 1 C S 0 1 1 0
A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C.
For a carry-in (Z) of , it is the same as the half-adder:
For a carry- in (Z) of 1: Z X 1
+ Y
+ 0
+ 1
C S
0 1
1 0 Z 1 X
+ Y
+ 0
+ 1
C S
0 1
1 0

21. the arithmetic sum of three input bits
Full-Adder :
the arithmetic sum of three input bits 
three input bits 
x, y: two significant bits 
z: the carry bit from the previous lower significant bit 
Two output bits: C, S  18

22. 19

23. S = x'y'z+x'yz'+ xy'z'+xyz C = xy + xz + yz S = zÅ (xÅy)
C = xy + xz + yz
S = zÅ (xÅy) 
= z'(xy'+x‘y)+z(xy'+x'y)'
= z‘xy'+z'x'y+z(xy+x‘y')
= xy'z'+x'yz'+xyz+x'y'z
C = z(xy'+x'y)+xy
= xy'z+x'yz+ xy 20

24. Binary adder
Note: n bit adder requires n full adders 21

25. Binary subtractor A-B = A+(2’s complement of B)
4-bit Adder-subtractor using M as mode of operation 
M=0, A+B; M=1, A+B’+1  26

26. Overflow The storage is limited Overfow cases :
Overfow cases :
1.Add two positive numbers and obtain a negative 
number
2. Add two negative numbers and obtain a positive
number 
V = 0, no overflow; V = 1, overflow 
Example:
Note: XOR is used to detect overflow. 27

27. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

28. 4-6 Decimal Adder Add two BCD's 9 inputs: two BCD's and one carry-in
9 inputs: two BCD's and one carry-in 
5 outputs: one BCD and one carry-out 
A truth table with 2^9 entries 
the sum <= = 19 
binary to BCD 

29. BCD Adder: The truth Table

30. In BCD modifications are needed if the sum > 9
Must add 6 (0110) in case: 
C = 1 
K = 1 
Z8z4=1  Z Z
= 1 
8 2 mo mo d
Ification when C=1 we add 6:  
C = K +Z Z + Z Z

31. Block diagram 

32. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

33. 4.7 Binary Multiplier Partial products
–use AND operations with half adder.
Note: A*B=1 only if A=B=1
Oherwise 0.
fig. 4.15
Two-bit by two-bit binary multiplier.

34. 4-bit by 3-bit binary multiplier
Fig. 4.16
Four-bit by three-bit binary
multiplier.
Digital Circuits

35. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

36. 4-9 Decoder A decoder is a combinational circute that converts n-input
lines to 2^n output lines.
We use here n-to-m decoder n 
a binary code of n bits = 2 distinct information n
n input variables; up to 2 output lines
only one output can be active (high) at any time

37. An implementation Fig. 4.18 Three-to-eight-line decoder.  38
Digital Circuits 38

38. Demultiplexers a decoder with an enable input receive information
a decoder with an enable input 
receive information 
in a single line and transmits
it in one of 2 possible output lines n
Fig. 4.19
Two-to-four-line decoder with enable input

39. Decoder Examples D0 = m0 = A2’A1’A0’ D1= m1 = A2’A1’A0 …etc
3-to-8-Line Decoder: example: Binary-to-octal conversion.
D0 = m0 = A2’A1’A0’
D1= m1 = A2’A1’A0
…etc

40. Expansion two 3-to-8 decoder: a 4-to-16 deocder a 5-to-32 decoder?
two 3-to-8 decoder: a 4-to-16 deocder 
Fig. 4.20
4 16 decoder
constructed with two
3 x 8 decoders
a 5-to-32 decoder? 

41. Decoder Expansion - Example 2
Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder. A0 A1 A2
3-8-line Decoder E
D0 – D7
D8 – D15
D16 – D23
D24 – D31
2-4-line Decoder A3 A4

42. Combination Logic Implementation
each output = a minterm 
use a decoder and an external OR gate to 
implement any Boolean function of n input
variables
A full-adder 
S(x,y,z)=S(1,2,4,7) 
C(x,y,z)=
C(x,y,z)= S S
(3,5,6,7)
(3,5,6,7)
Fig. 4.21
Implementation of a full adder with 1 decoder

43. two possible approaches using decoder
OR(minterms of F): k inputs 
NOR(minterms of F'): 2 - k inputs n 
In general, it is not a practical implementation 

44. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

45. 4.10 Encoders The inverse function of decoder a decoder z = D + D + D
a decoder z = D + D + D + D
The encoder can be implemented y = D + D + D + D
with three OR gates. x = D + D + D + D

46. An implementation limitations illegal input: e.g. D =D x1
limitations 
illegal input: e.g. D =D x1 
3 6
The output = 111 (¹3 and ¹6) 

47. Priority Encoder resolve the ambiguity of illegal inputs
only one of the input is encoded  D
has the highest priority  3 D
has the lowest priority 
X: don't-care conditions 
V: valid output indicator 

48. ■ The maps for simplifying outputs x and y
fig. 4.22
Maps for a priority encoder

49. ■ Implementation of priority
x =
Fig. 4.23 D + D
2 3
Four-input priority encoder y= D +
D D V = D + D + D + D

50. Outline:
4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders Encoders Multiplexers.

51. 4.11 Multiplexers select binary information from one of many input
lines and direct it to a single output line
2 input lines, n selection lines and one output line n 
e.g.: 2-to-1-line multiplexer 
Fig. 4.24
Two-to-one-line multiplexer

52. 4-to-1-line multiplexer
Fig. 4.25
Four-to-one-line multiplexer

53. Note n-to- 2 decoder add the 2 input lines to each AND gate
add the 2 input lines to each AND gate n 
OR(all AND gates) 
an enable input (an option) 

54. Fig. 4.26
Quadruple two-to-one-line multiplexer

55. Boolean function implementation
MUX: a decoders an OR gate  n
2 -to-1 MUX can implement any Boolean function 
of n input variable
a better solution: implement any Boolean function
of n+1 input variable 
n of these variables: the selection lines
the remaining variable: the inputs

56. an example: F(A,B,C) = S(1,2,6,7)
an example: F(A,B,C) = S(1,2,6,7)
Fig. 4.27
Implementing a Boolean function with a multiplexer

57. Procedure: Assign an ordering sequence of the input variable
Assign an ordering sequence of the input variable 
the rightmost variable (D) will be used for the input 
lines
assign the remaining n-1 variables to the selection 
Lines with construct the truth table
lines w.r.t. their corresponding sequ 
consider a pair of consecutive minterms starting 
from m
determine the input lines 

58. Example: F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15) Fig. 4.28
Implementing a four-input function with a multiplexer

59. Three-state gates A multiplexer can be constructed with three-state
A multiplexer can be constructed with three-state
gates
Output state: 0, 1, and high-impedance (open ckts) 
Fig. 4.29
Graphic symbol for a three-state buffer

60. Example: Four-to-one-line multiplexer
Fig. 4.30
Multiplexer with three-state gates