1. CS 141 ChienMay 26, 1999 Interrupt-Driven Input/Output u Last Time –Busses, Arbitration, Interoperability –Polled Input/Output Operations –Inefficiencies u This Time –Interrupts –Interrupt-Driven I/O –Serial and Block Device Examples u Reminders/Announcements –Reading P&H, Chapter 8.5-8.9 –Next week, 6/4 Course Review –Final Exam, 6/7, 8-11am (location tbd) –HW4 due on 6/4 (in class)

2. CS 141 ChienMay 26, 1999 Exceptions and Interrupts u Exceptions cause a control transfer to an exception handler in response to an unusual event. –Ex. floating point overflow, memory addressing error, segmentation fault, etc. u This control transfer looks like a “Dynamic Procedure call” u Exceptions are caused by the executing instruction(s) –Happen “at a particular instruction” –One handler for each exception, “vectored exceptions” u Handler decodes the exception based on stored status info (PC, exception register, etc.), and performs appropriate action

3. CS 141 ChienMay 26, 1999 Interrupts u Interrupts = “externally caused exceptions” u Dynamic Procedure call (same as an internal exception) u Have NOTHING to do with current execution, not synchronized with instruction stream, so delays can be tolerated. u Interrupt -> “interrupts” what the processor is doing Interrupt Processor Exception

4. CS 141 ChienMay 26, 1999 Interrupt Example u External Device causes interrupt u Executing code is stopped, dynamic procedure call –Delay doesn’t matter much u State is saved (as with an exception), control is passed to the “interrupt handler” u After servicing interrupt, control returned to previously running program Processor Interrupt Controller I/O Device inst0 inst1 inst2 inst3 inst4... ihandler:instA instB instC rte

5. CS 141 ChienMay 26, 1999 Using Interrupts for Input/Output u Why are interrupts useful? –External analogy to exceptions –Allow response to unusual external events without inline overhead (polling). u Idea: Use interrupts to reduce polling overhead for Input/output –Processor initiates I/O operation –Device interrupts processor when its ready –Interrupt handler transfers data into the memory –Control returned to currently executing program u Analogous schedule for output operations u Polling overhead vs. Interrupt handling cost

6. CS 141 ChienMay 26, 1999 Advantages &Complications u Advantages –Reduced polling time vs. interrupt cost –Improved program modularity (no more polling code) –Preserves the ability of old programs to run in new configurations u Complications –Additional hardware required (interrupt controller, etc.) –How to deal with several devices? –What if more than one interrupt occurs at once? u We’ll deal with these questions next.

7. CS 141 ChienMay 26, 1999 Multiple sources of Interrupts u How to determine which device caused the interrupt? –Single device per priority –Devices place their ID number on the address bus –Processor polls devices to find out which caused the interrupt –Interrupt Handler -> reads some hardware status registers to determine the source of the interrupt u How to handle an interrupt within an interrupt? –Many systems don’t; disable interrupts when within an interrupt handler –Some systems have interrupt priorities, while in an interrupt handler; only a higher priority interrupt will be handled

8. CS 141 ChienMay 26, 1999 Interrupt Handler Structure u Disable Interrupts u Determine device causing interrupt u Do appropriate processing u Enable Interrupts u What does the stack look like during the interrupt? –stuff on stack before interrupt –stack frame for the interrupt handler? Special return instruction (rte) –when can you allocate stack frame memory? (when is it safe?) inthandler: disableInts lw $2,device($0)... do the work... enableInts rte

9. CS 141 ChienMay 26, 1999 Interrupts and Response Time u Lower numbers are “higher priority” u How should we assign priorities to devices? –Latency is critical for some devices. –Ordering can have big impact on latency. u Assume non-preemptive priority system. –Interrupts cannot be interrupted. –Pending interrupts are processed in order of priority. Device NumberInterrupt Priority -------------------------------------------- 03 122 31

10. CS 141 ChienMay 26, 1999 Guaranteed Maximum Latency Guaranteed Maximum ( I )= MAX(service time of devices at I) Latency+ SUM(service time of devices with greater priority) Device NumberInterrupt PriorityServiceGuar. Max. Latency -------------------------------------------- ---------- -------------------------- 03 10 12 10 22 10 31 10

11. CS 141 ChienMay 26, 1999 Real-Time Systems (Embedded systems) u Timeliness of response is fundamental requirement of system design –Control (cars, airplanes, manufacturing) –Instrumentation (measurement, data capture) –Tracking, Guidance (military apps) –Otherwise, system fails! u Real-Time requirements fundamentally affect the nature of system design.

12. CS 141 ChienMay 26, 1999 Interrupt-Driven I/O (Overview) u Processor sets up I/O operation, continues its work u Device performs I/O (a long time) u Device completes, interrupts the processor u Processor responds to interrupt, transfers the data u I/O is complete. u => Interrupts save overhead of polling. PMem I/O Memory Bus I/O Bus

13. CS 141 ChienMay 26, 1999 Summary u Interrupts as external exceptions u Interrupt Handling u Motivation for Interrupt-Driven Input/Output u How Interrupt-Driven Input/Output works u Next time: How to make I/O even more efficient (DMA)! u Where is there still overhead? (data movement) –Size of data transfers? Cost?