1. Processes of Fabrication

2. N Transistor Structure Review

3. P Transistor Structure Review

4. Semiconductor Review Create by doping a pure silicon crystal
Diffuse impurity into crystal lattice
Changes the concentration of carriers
Electrons
Holes
More doping -> more carriers available
n-type semiconductor (n or n+)
Majority carrier: electrons
Typical impurity: Arsenic (Column V)
p-type semiconductor (p or p+)
Majority carrier: holes
Typical impurity: Boron (Column III) n+ n p+ p

5. Other key working materials
Insulator - Silicon Dioxide (SiO2)
Used to insulate transistor gates (thin oxide)
Used to insulate layers of wires (field oxide)
Can be grown on Silicon or Chemically Deposited
Polysilicon - polycrystalline silicon
Key material for transistor gates
Also used for short wires
Added by chemical deposition
Metal - Aluminum (…and more recently Copper)
Used for wires
Multiple layers common
Added by vapor deposition or “sputtering”

6. CMOS Processing Wafer Processing Photolithography
Oxide Growth & Removal
Material Deposition & Removal
Diffusion of Impurities
Putting it all together

7. AMD’s Dresden Fab - Source: AMD Corporation www.amd.com
A View of the Cleanroom
AMD’s Dresden Fab - Source: AMD Corporation

8. Creating Wafers - Czochralski Method
Crucible
Molten
Silicon
Start with crucible of molten silicon (≈1425oC)
Insert crystal seed in melt
Slowly rotate / raise seed to form single crystal boule
After cooling, slice boule into wafers & polish

9. Definitions Wafer – a thin circular silicon
Each wafer holds hundreds of dies
Transistors and wiring are made from many layers (usually 10 – 15) built on top of one another
the first half-dozen or so layers define transistors
the second define the metal wires between transistors
Lambda () – the smallest resolvable feature size imprinted on the IC; it is roughly half the length of the smallest transistor
0.2m IC – the smallest transistors are approximately 0.2m in length (= 0.1m)

10. Wafer Structure Current production: 200mm (10”)
Newest technology: 300mm (12”)

11. Processing Wafers All dice on wafer processed simultaneously
Each mask has one image for each die
The basic approach:
Add & selectively remove materials
Metal - wires
Polysilicon - gates
Oxide
Selectively diffuse impurities
Photolithography is the key

12. Fabrication processes
IC built on silicon substrate:
some structures diffused into substrate;
other structures built on top of substrate.
Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal).
Silicon dioxide (SiO2) is insulator.

13. Photolithography Coat wafer with photoresist (PR)
Shine UV light through mask to selectively expose PR
Use acid to dissolve exposed PR
Now use exposed areas for
Selective doping
Selective removal of material under exposed PR
Mask
UV Light
Photoresist
Wafer

14. Adding Materials Add materials on top of silicon Methods Polysilicon
Metal
Oxide (SiO2) - Insulator
Methods
Chemical deposition
Sputtering (Metal ions)
Oxidation

15. Oxide (Si02) - The Key Insulator
Thin Oxide
Add using chemical deposition
Used to form gate insulator & block active areas
Field Oxide (FOX) - formed by oxidation
Wet (H20 at 900oC oC) or Dry (O2 at 1200oC)
Used to insulate non-active areas
SiO2 Thin Oxide
FOX
SiN / SiO2
Silicon Wafer

16. Patterning Materials using Photolithography
Add material to wafer
Coat with photoresist
Selectively remove photoresist
Remove exposed material
Remove remaining PR

17. Diffusion
Introduce dopant via epitaxy or ion implant e.g. Arsenic (N), Boron (P)
Allow dopants to diffuse at high temperature
Block diffusion in selective areas using oxide or PR
Diffusion spreads both vertically, horizontally

18. CMOS Well Structures Need to accommodate both N, P transistors
Must implement in separate regions - wellls (tubs)
N-well
P-well
Alternate approach: Silicon on Insulator (SOI)
n-well
p substrate
n well
n substrate
p well
p-well

19. Detailed View - N-Well Process
Overall chip doped as p substrate, tied to GND
Selected well areas doped n, tied to VDD
Gnd
VDD

20. CMOS Processing - Creating an Inverter
Substrate
Well
Active Areas
Gates
Diffusion
Insulator
Contacts
Metal
P substrate
n well
wafer

21. CMOS Mask Layers Determine placement of layout objects
Color coding specifies layers
Layout objects:
Rectangles
Polygons
Arbitrary shapes
Grid types
Absolute (“micron”)
Scaleable (“lambda”)
P substrate
n well
wafer

22. Mask Generation Mask Design using Layout Editor Pattern Generator
user specifies layout objects on different layers
output: layout file
Pattern Generator
Reads layout file
Generates enlarged master image of each mask layer
Image printed on glass reticle
Step & repeat camera
Reduces & copies reticle image onto mask
One copy for each die on wafer
Note importance of mask alignment

23. Simple cross section SiO2 metal3 metal2 metal1 transistor via poly n+
substrate n+ p+
substrate

24. Transistor structure
n-type transistor:

25. 0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly

26. Fabrication and Layout
Ion Implantation
Focus
Neutral beam and
beam path gated
Beam trap and
gate plate
Wafer in wafer
process chamber
X - axis
scanner
Y - axis
Neutral beam trap
and beam gate
Process Conditions
Flow Rate: 5 sccm
Pressure: Torr
Accelerating Voltage: 5 to 200 keV
Gases Ar
AsH3
B11F3 * He N2
PH3
SiH4
SiF4
GeH4
Solids Ga In Sb
Liquids
Al(CH3)3
180 kV
Resolving
Aperture
Ion Source
Equipment Ground
Acceleration Tube
90° Analyzing Magnet
Terminal Ground
20 kV
Fabrication and Layout

27. Fabrication and Layout
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
Fabrication and Layout

28. Fabrication and Layout
Polysilicon
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Fabrication and Layout

29. Polysilicon Patterning
Use same lithography process to pattern polysilicon
Fabrication and Layout

30. Fabrication and Layout
Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
Fabrication and Layout

31. Fabrication and Layout
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing
Fabrication and Layout

32. Fabrication and Layout
N-diffusion
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
Fabrication and Layout

33. Fabrication and Layout
N-diffusion
Strip off oxide to complete patterning step
Fabrication and Layout

34. Fabrication and Layout
P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
Fabrication and Layout

35. Fabrication and Layout
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Fabrication and Layout

36. Fabrication and Layout
Metallization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Fabrication and Layout

37. Physical Vapor Deposition (PVD)
Chambers
Cluster Tool
Configuration
Process Conditions
Pressure: < 5 mTorr
Temperature: 200 degrees C.
RF Power:
Wafers
Transfer
Chamber
Loadlock
Barrier Metals
SiH4 Ar N2
Ti PVD Targets *
Reactive
Gases
PVD Chamber N S
Cryo Pump
Transfer
Chamber
e - +
Wafer
Argon &
Nitrogen
Backside
He Cooling
DC Power
Supply (+)
Fabrication and Layout

38. Schematic Diagram of Vacuum Evaporation System (PVD)
Fabrication and Layout

39. Fabrication and Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
Fabrication and Layout

40. Simplified Design Rules
Conservative rules to get you started
Fabrication and Layout

41. Fabrication and Layout
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4l / 2l, sometimes called 1 unit
For 0.6 mm process, W=1.2 mm, L=0.6 mm
Fabrication and Layout

42. Fabrication and Layout
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start designing schematics and layout for a simple chip!
Fabrication and Layout