1. Mini-Lecture 8 Intellectual Property

2. Agenda Discussion of Lab7 Solutions and lessons learned Intellectual Property Description of class agenda from this point until the end of the semester Final Project discussion

3. Synthesis Results (Lab7) # BELS : 44 # GND : 1 # LUT2 : 3 # LUT3 : 36 # LUT3_D : 2 # LUT4 : 1 # VCC : 1 # FlipFlops/Latches : 35 # FDC : 3 # FDE : 32 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 132 # IBUF : 66 # OBUF : 66 # DSPs : 1 # DSP48 : 1 267MHz Estimated

4. Simple Behavioral VHDL Example entity beh is port (a : in signed (15 downto 0); b : in signed (15 downto 0); c : out signed (31 downto 0); clk : in std_logic; rst : in std_logic; mode : in std_logic_vector(1 downto 0) ); end beh; process(clk,rst) begin if rst = '1' then p '0'); elsif rising_edge(clk) then if mode = "00" then p <= a*b; elsif mode = "01" then p <= p+a*b; elsif mode = "10" then p <= p-a*b; elsif mode = "11" then p <= -a*b; end if; end process;

5. Results : Cell Usage : # BELS : 162 # GND : 1 # LUT2 : 2 # LUT4 : 95 # MUXCY : 31 # VCC : 1 # XORCY : 32 # FlipFlops/Latches : 32 # FDCE : 32 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 67 # IBUF : 35 # OBUF : 32 # DSPs : 1 # DSP48 : 1 Est : 287 MHz

6. References: Some articles on writing behavioral code to make use of the DSP48 –http://www.mvd-fpga.com/en/publi_V4_DSP48.html –http://www.xilinx.com/publications/xcellonline/xcell_55/xc_rtlcode55.htmhttp://www.xilinx.com/publications/xcellonline/xcell_55/xc_rtlcode55.htm Emphasizes the fact that in order to make good use of FPGA resources with our code we: –Need to understand the FPGA target architecture –Need to be aware of the technology built by synthesis tools –Need to be flexible with different coding styles Instantiation vs. inference Modifying the style and functionality in order to best utilize the real resources

7. Intellectual Property – FPGAs are huge! Current FPGAs, particularly RAM-based devices such as the Xilinx Virtex series and the Altera Statix, are large enough that they can hold significant system components, such as bus interfaces, processors, DSP blocks, communications standards, and large blocks of custom logic. However, to use the ocean of resources available in a current FPGA by developing system components in- house takes a large design team with expertise in a range of areas, as well as an overwhelming amount of testing.

8. Intellectual Property For this reason, intellectual property is now a widely used method for FPGA development, where definitions of system components at some stage in the implementation flow can be purchased for use in an FPGA. –Where in the implementation flow is important: remember than plain vanilla behavioral vhdl code doesnt always utilize FPGA special structures effectively In fact, multiple components can be integrated with custom logic on an FPGA to build an entire system- on-a-chip (SOC) or, in the case of an FPGA, System- on-Programmable-Chip –Interesting to note that FPGAs (as a big version of a PLD) were used to replace glue logic, TTL logic, etc.) while now they are being used to replace uPs

9. IP Core Sources 1.From the chip vendor (i.e., Xilinx, Altera IP Megastore, Aldec) for common cores Consider Xilinx CORE Generator: many free cores and evaluation versions, also supports purchasable cores: Ethernet MAC, USB, CAN (Controller Area Network, a bus standard), PCI, FFT, FIR filter, DDS, etc. 2.Additional vendors specializing in particular areas: Dillon Engineering makes ultra-long FFT cores – they actually will implement them in your particular device 3.For free: for example see www.opencores.org

10. Intellectual Property Delivery Intellectual property for FPGAs generally comes in two different forms: –an encrypted netlist (synthesized prior to encryption) which effectively prevents the design from being modified (it is encrypted to prevent sections of the IP from being copied) –as a register-transfer-logic (RTL) HDL description that can be modified. These types of cores are known as "soft," since they must still undergo the place-and- route portion of the FPGA implementation flow. At times, high performance cores (such as optimized processors) come as a post-place- and-route netlist that is designed to fit in a particular section of an FPGA. –Known as a hard core, since its location within the FPGA is already determined. –As recently as three years ago, even a PCI core would come in this form to guarantee timingas FPGAs have become larger and faster, this is no longer necessary. –Note an embedded processor (such as Xilinxs MicroBlaze is not the same. Also there are cores actually installed in the fabric, like the PowerPC in a Virtex-4. RTL Model Gate-level Model Synthesize FPGA Place & Route RTL Design Encrypted Netlist Hard IP Core Timing Model FPGA Design Flow IP Core Type

11. Advantages of IP The advantages of using intellectual property are: 1.reduced design risk 2.shorter test and debug cycles 3.increased integration 4.design reuse These translate to additional advantages for flight hardware (for those of you interested): 5.lower power and smaller size due to increased integration 1.Flight hardware uses more discrete system components because old technology is used since reliability is of highest import 6.smaller form factors due to the shrinking size of FPGAs 7.future reusability, which can eliminate heritage issues; 8.an easy way to gain radiation hardened system components (in fact, most flight processors are now built by implementing a processor IP core in an ASIC fabricated with a rad-hard process).

12. Disadvantages of IP In general, the main disadvantage of using IP is that it encourages overly aggressive scheduling. –IP is often advertised as offering a nearly turn-key solution to design problems, and, in fact, it can be in common-place situations –Good if you need a common-place solution –(flight hardware tends to make even the common-place situations uncommon). In general, IP use requires a large amount of knowledge of the cores technology, time to become familiar with a particular cores operation, and time to test the final FPGA. This disadvantage (encouraging overly-aggressive scheduling) cannot be over-estimated! If a core is useful, it is probably large enough that it cannot be fully understood w/o an investment of time…

13. Additional Disadvantages For flight hardware in particular, an additional disadvantage of using IP is in the effort required to evaluate if a core is safe for space. –Digital designs for flight hardware must be as single-event-upset (SEU) immune as possible, with safe state machines, registers that refresh, and triple-voted flip-flops. –Note that some of these concerns may be provided by the internal structure of the FPGA for example, the Actel R54SX32S has triple-voted flip-flops that refresh every clock cycle. It would be nearly impossible to evaluate an IP core not delivered as an RTL description. –Even when a core is delivered as an RTL HDL description, evaluation for flight applications can be difficult due to its size. –Presumably, the design is large enough to make it worth purchasing a core, rather than designing a full solution in-house. Triple-Voted Flip-Flop as Implemented in Actel FPGA

14. Skew Problem The final thing to remember with IP: –purchasing IP cores, even when the core itself is perfect, is not equivalent to buying a working part. Even if an IP core easily integrates with the rest of the system, the physical implementation of the FPGA can have significant problems. A clock skew problem was found in the RT54SX32S device that was not reported in the Actel Timer software (part of the Actel Designer suite). Although this was found in the custom backend, the fault was not that of the logic design, and there is nothing to prevent it from having occurred in the IP core. Waveform of skew problem taken from Logic Analyzer. The arrow marked Double-Shift denotes where the problem can be observed.

15. Points to Remember when Using IP 1.Intellectual property can allow a system and design to be optimized for speed, the particulars of the system, etc. This is a significant benefit. 2.Intellectual property can protect an organization from heritage problems. A RTL IP combined with custom HDL is rather portable and can be implemented in future FPGAs, even as new devices are introduced. 3.IP can enable greater integration. As technologies mature, multiple independent FPGAs can be merged into a single device. 4.Purchasing IP replaces a host of design work, but does not offer a turn-key solution. 5.If a core is not in RTL format, it can be difficult to evaluate for quality, and can be difficult to debug if errors appear. 6.Buying a core that is independently certified will likely go a long way towards guaranteeing success. 7.IP is not like buying a working parteven if the logic is perfect, a whole host of problems can prevent it from working properly. 8.If an IP core comes with a great testbench, its value increases dramatically. Of course, simulation is not a replacement for physical testing. Good documentation also affects the value dramatically.

16. CoreGen to Create Customizable IP IP must be highly parameterized to be useful to as many users as possible –Make extensive use of generics and generates Using IP may involve instantiating a component and setting all the appropriate generics (i.e. learning how to use it from the datasheet) Xilinx COREGEN tool provides a menu driven interface to create a wrapper for the raw IP, letting you build your component the way you like it.

17. Create a new source which is the IP that you want to use in your project. Xilinx will create a.xco file which contains all the settings, as well as the necessary netlist and simulation files.

18. A link to a pdf data sheet which describes how the core works, much like a chip data sheet. Often contains device utilization, speed…etc.

19. ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG component my_complex_multiplier port ( ar: IN std_logic_VECTOR(23 downto 0); ai: IN std_logic_VECTOR(23 downto 0); br: IN std_logic_VECTOR(23 downto 0); bi: IN std_logic_VECTOR(23 downto 0); round_cy: IN std_logic; pr: OUT std_logic_VECTOR(31 downto 0); pi: OUT std_logic_VECTOR(31 downto 0); clk: IN std_logic; ce: IN std_logic; sclr: IN std_logic); end component; -- Synplicity black box declaration attribute syn_black_box : boolean; attribute syn_black_box of my_complex_multiplier: component is true; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ -- The following code must appear in the VHDL architecture -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : my_complex_multiplier port map ( ar => ar, ai => ai, br => br, bi => bi, round_cy => round_cy, pr => pr, pi => pi, clk => clk, ce => ce, sclr => sclr); -- INST_TAG_END ------ End INSTANTIATION Template ------------ -- You must compile the wrapper file my_complex_multiplier.vhd when simulating -- the core, my_complex_multiplier. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". My_complex_multiplier.vho

20. ADC/DAC time voltage DAC: digital value to voltageADC: voltage to digital value

21. DDS Lite Direct Digital Synthesis is a mostly digital technique for generating an output waveform (sine, square or triangular) or clocking signal from a fixed-frequency clock source. For more on DDS http://sss-mag.com/pdf/synthbk.pdf Phase Accum SINE LUT D/A Low-pass Filter Phase step size FPGA CODEC

22. DDS Lite Our DDS will use intellectual property for the SINE LUT and the D/A, which we will move into the FPGA Phase Accum SINE LUT Low-pass Filter Phase step size FPGABread-board D/A

23. Generating a Sine Wave Say our sample rate is 8khz, and our table has 16 points. Incrementing by 1: 8 kHz/16 = 500Hz Incrementing by 2: 8 kHz/(16/2) = 1 kHz Incrementing by 3: 8 kHz/(16/3) = 1.5 kHz

24. Block Diagram Sine table (IP) sample-rate generator Phase accumulator Shift DAC (IP) Switches[2:0]Switches[5:3] 1-bit output

25. Modelsim Simulation

26. Delta-Sigma: XAPP154 Delta-Sigma DAC: –Uses digital techniques, which makes it impervious to temperature change, and may be implemented in programmable logic –Are over-sampled single-bit DACs (i.e., the output is a digital value at either VCC or ground). –Using digital feedback, a string of pulses is generated. The average duty cycle of the pulse string is proportional to the value of the binary input. –The analog signal is created by passing the pulse string through an analog low-pass filter. –Delta-Sigma DACs are used extensively in audio applications. They are suited for low frequency applications that require relatively high accuracy.

27. Delta-Sigma: Middle Range Low pass filter averages, in this case to VCC/2

28. Delta-Sigma: Upper Range

29. Delta-Sigma: Lower Range