1. Chapter 7 8086/8088 Hardware Specifications
Microprocessors
Chapter 7
8086/8088 Hardware Specifications
prepared by
Dr. Mohamed A. Shohla

2. Chapter Overview Pin-Outs and the Pin Functions
Bus Buffering and Latching
Bus Timing

3. Pin-Outs and the Pin Functions
the 8086 is a 16-bit microprocessor with a 16-bit data bus, and the 8088 is a 16-bit microprocessor with an 8-bit data bus. (As the pin-outs show, the 8086 has pin connections AD0-AD15, and the 8088 has pin connections AD0-AD7.)
Data bus width is therefore the only major difference between these microprocessors.
There is, however, a minor difference in one of the control signals.
The 8086 has an pin, and the 8088 has an pin.
The only other hardware difference appears on Pin 34 of both chips: on the 8088, it is an SSO pin, while on the 8086, it is a pin.

4. Pin Connections

5. Function of status bits S3 and S4.

6. Minimum Mode Pins

7. Bus cycle status (8088) using

8. Maximum Mode Pins
The status bits indicate the function of the current bus cycle. These signals are normally decoded by the 8288 bus controller described later in this chapter.

9. Bus Buffering and Latching
Before the 8086/8088 microprocessors can be used with memory or I/O interfaces, their multi­plexed buses must be demultiplexed.
This section provides the detail required to demultiplex the buses and illustrates how the buses are buffered for very large systems.

10. Demultiplexing the Buses of the 8088
Two 74LS373 transparent latches are used to demulti­plex the address/data bus connections AD7-AD0 and the multiplexed address/status connections A19/S6-A16/S3.
These transparent latches, which are like wires whenever the address latch enable pin (ALE) becomes a logic 1, pass the inputs to the outputs. After a short time, ALE returns to its logic 0 condition, which causes the latches to remember the inputs at the time of the change to a logic 0.
In this case, A7-A0 are stored in the bottom latch and A19-A16 are stored in the top latch.

11. Demultiplexing the Buses of the 8088

12. Demultiplexing the Buses of the 8086

13. The Buffered System
If more than 10 unit loads are attached to any bus pin, the entire 8086 or 8088 system must be buffered.
The demultiplexed pins are already buffered by the 74LS373 latches, which have been designed to drive the high-capacitance buses encountered in microcomputer systems.
The buffer's output currents have been increased so that more TTL unit loads may be driven: a logic 0 output provides up to 32 mA of sink current, and a logic 1 output provides up to 5.2 mA of source current.
This causes no difficulty unless memory or I/O devices are used, which function at near the maximum speed of the bus.

14. The Fully Buffered 8088

15. The Fully Buffered 8086

16. Basic Bus Operation
Simplified 8086/8088 write bus cycle

17. Basic Bus Operation
Simplified 8086/8088 read bus cycle