1. The Fetch Execute Cycle
The fetch – execute cycle has 2 phases:
The fetch phase is where the instruction is copied into the control unit and decoded (memory READ operation)
The execute phase is where the instruction is carried out (memory WRITE)

2. Memory READ Operation 0000 1101 1101 READ CU
Arithmetic and Logic Unit (ALU)
Other registers
MAR
MDR
DATA
Address bus
Data bus
Control Bus (Read / Write)
Electronic clock
Clock pulses
1001
0001
1000
0111
1010
0110
0100
0101
0010
1111
0011
1011
0000
1101
ADDRESS
Memory READ Operation
0000
1101
1101
READ

3. Memory READ Operation 1. Memory Read Operation
CPU sets up address bus by placing a value in the Memory Address Register
The Control Unit activates the read line on the control bus
The contents of the storage location are released onto the data bus and copied into the CPU’s Memory Data Register

4. Memory WRITE OperationCU
Arithmetic and Logic Unit (ALU)
Other registers
MAR
MDR
DATA
Address bus
Data bus
Control Bus (Read / Write)
Electronic clock
Clock pulses
1001
0001
1000
0111
1010
0110
0100
0101
0010
1111
0011
1011
0000
1101
ADDRESS
Memory WRITE Operation
0101
1111
1111
1111
WRITE

5. Memory WRITE Operation
CPU sets up the address bus by placing the required memory address in the Memory Address Register
CPU sets up the data bus by placing the value to be written in the Memory Data Register
The control unit activates the write line on the control bus
The contents of the MDR are transferred to the required storage location in memory