1. D Flip-Flop

2. Lecture Overview D Flip-Flops Logic Synchronization
Types of D Flip Flops
Sample Flip-Flop Applications

3. Positive Edge Triggered
D Flip-Flop
CLK 
Q n+1 1 D
Positive Edge Triggered
D Q Q
CLK D Q

4. Logic Synchronizing Data enters here at different times
Example:
Parallel Port
Data enters here at different times
Data goes out at the same time on a clock pulse

5. Types of D Flip-Flops D Q Q Positive Edge Triggered
Negative Edge Triggered
D Q Q

6. Types of D Flip-Flops D Q Q Positive Level Triggered D Q Q
Negative Level Triggered

7. Asynchronous Inputs D Q Q D Flip-Flop w/ Preset D Q Q
P-SET
D Flip-Flop w/ Clear
D Q Q
CLR

8. Asynchronous Inputs
D Flip-Flop w/ Preset & Clear
D Q Q
P-SET
CLR

9. D Flip-Flop w/ Preset & Clear
Q n+1
1 (preset)
0 (clear)
? (illegal) 1
CLK X  D
CLR
P-SET
D Q Q
P-SET
CLR

10. Application of D Flip-Flops
Data Storage
Counters & State Machine Designs
Logic Synchronizing
Divide By Circuits

11. Divide By Circuit with D Flip-Flop

12. Divide By Circuit - Simulation