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SCT has developed a new ATLAS trigger card Introduction Concept & Motivation Functionality Overview Production Status ATLAS orders 03/05/20111Dave Robinson.

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Presentation on theme: "SCT has developed a new ATLAS trigger card Introduction Concept & Motivation Functionality Overview Production Status ATLAS orders 03/05/20111Dave Robinson."— Presentation transcript:

1 SCT has developed a new ATLAS trigger card Introduction Concept & Motivation Functionality Overview Production Status ATLAS orders 03/05/20111Dave Robinson Atlas weekly run meeting

2 What is it? 6U VME Digital Atlas VmeElectronics (DAVE) card (acronym reflects a certain sense of humour by our engineers) Design, production and firmware by UCL and Cambridge – Maurice Goodrick, Rick Shaw (Cambridge) – Matt Warren, Martin Postranecky (UCL) Support and encouragement from ATLAS – Strong support and ideas from ThiloPauly, Carolina Gabaldone – User case suggestions from IskanderIbragimov, Bruce Barnett, Andrej Gorisek 03/05/20112Dave Robinson Atlas weekly run meeting

3 Concept & Motivation 03/05/2011Dave Robinson Atlas weekly run meeting3 Delay Stretch Pulse Generator Trigger Orbit (BCR) L1A to LTP NIM Crate – SCT USA15 VETO We long wanted to eliminate use of a NIM crate in USA15 which provides our trigger for standalone physics runs Contains veto logic (prevent BCR/L1A clash) which drifts Need to go downstairs to adjust trigger rate Non-realistic conditions First thoughts were replace this simple logic in a VME card Concept quickly grew to add more generic features Significant enhancement to adopt ATLAS CTP functionality to exactly duplicate running conditions, whilst incorporating much generic functionality, has evolved the card into a powerful and flexible logic card, potentially useful to all ATLAS subsystems as well as for non-ATLAS use

4 DAVE card: examples of CTP Functionality 4 ECRsel VME ECRin period 8 PS MSK Gate Veto OR 8 8 SHP ExtTrigger 8 4 1 1 L1Aout TriggerOut SD CD OR BUSY L1Ain 1+1m s ECRsel ECRout L1Aout Veto Internal Playback Fixed Freq RND BG 2 2 4 6? Internal VCXO BCout BCin DELAY25 QPLL? internal ORBin ORBout 03/05/2011Dave Robinson Atlas weekly run meeting

5 Interesting use-cases Trigger generator for LTP (via LEMO) – no busy gating, feed-forward of deadtime to LTP Standalone trigger generator without LTP – busy gating ECR generator VETO generator L1A (or other signal) sequence analyser Sequence playback – Eg capture and replay trigger sequences that causes susbsystem busy etc BC/ORBIT source, fine-delay (dt=0.5-1ns) for timing scans Generic delay line Generic counter facility – a few counters – per-bunch counters? Generic logic unit – Programmable “NIM crate” 503/05/2011Dave Robinson Atlas weekly run meeting SCT Use: Trigger generator to LTP via lemo Programmable random rate up to 100kHz BGS appropriate to take care of BCR/L1A clash feed-forward of deadtime (simple/complex) to LTP

6 3x LEDs NIM ECL 12x LEDs 3 3 3 3 3 SHIFT REG. 2 CLKIN0 IN0 IN2 IN6 IN4 CLKIN1 CLKOUT0 OUT0 OUT2 OUT6 OUT4 CLKOUT1 SW 2 2 88 2 2 8 8 NIM ECL NIM TTL NIM TTL HEX SELECT 16-pin AUX. CONNECTOR USB J - TAG X-TAL 80.15733MHz MPX PLL :2 40/80MHz select CLK Master DELAY 4x Slave DELAYS4 4 4 CLKIN select FPGA & PROM 2 8 4 8 16 6 2 16 ( incl. 4x 2V5 diff. LVDS ) SW SERIAL NO. MOD. RECORD SW 24 40-pin DIL BREAK-OUT HEADER All POWER and GND rails 32 EXT. +5V IN FUSES +3V3 +2V5 +1V8 +1V2 -5V -2V 6x DC-DC VME J1 VME J2 +5V FUSE Buffers VME BASE ADDRESS 16 22 Data 4Mbx18 SRAM Address MP-UCL, 21 February 2011 20x LEMO-00 Buffers All POWER Monitor 7 7 2x LEDs ATLAS-SCT “DAVE-1” Programmable VME Module M.Goodrick, D.Robinson,R.Shaw @ University of Cambridge, Cavendish LabM.Postranecky, M.Warren @ UCL 7 8 8 SHIFT REG. 6 FPGA spec: Xilinx Spartan 3E 1600 (SC3S1600E) 03/05/2011Dave Robinson Atlas weekly run meeting

7 7 DAVE card – first prototype 03/05/2011Dave Robinson Atlas weekly run meeting

8 CTP-like Trigger Module DAVE card Firmware Blocks AND/OR matrix Input Enable Sync Delay 8 Busy Gen Output Enable Map Internal Sig Gen Randomiser Fixed Freq BCR/BCID ECR/ECRID Sequencer ECR Gen BCR Gen Fine Delay* 63x.5ns Mask/ Gate Dead-time Not on FPGA using CERN Delay25 chip 4 Sink RAM VME/USB Interface 8 LEMO In LEMO Out Firmware mainly by Matt, USB by Maurice, testing by Rick CTP blocks originally by Stefan Haas. Higher level software to be provided by ThiloPauly and/or Dave Robinson 03/05/20118Dave Robinson Atlas weekly run meeting

9 Production 3 prototypes already built Jan/Feb – Some minor design iterations were identified Corrections made by wire-tack Firmware already well underway and some basic functionality demonstrated – USB functionality still pending Final design iterations in place Production is underway A further 17 production modules to be built – Delivery by late summer Production cost ~ 1.6K CHF per module 03/05/2011Dave Robinson Atlas weekly run meeting9

10 ATLAS Orders SCT TRT Pixels BCM ATLAS central trigger Strong interest by L1Calo and LAr …others are likely? – Interest too from outside ATLAS! 03/05/2011Dave Robinson Atlas weekly run meeting10

11 Summary - Key Points Communication by VME or USB – In vme/TTC crate or on desktop with power supply Exact CTP functionality – Random trigger, simple and complex deadtime, ECR, BCR etc to give exact same conditions in standalone as experienced in combined runs Trigger sequence playback – 64M word SRAM gives us up to 52 seconds history of trigger playback for 75kHz L1 rate (eg on interrupt by system BUSY) Powerful generic functionality Available by late summer … when you will see them in TTC crates in USA15! 03/05/2011Dave Robinson Atlas weekly run meeting11

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