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Microprogramming A Case Study
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ITSIAC Accumulator register, ACC, for arithmetic operations.
Instruction has Operation code and storage address, A. (A) means "the contents of location A" The CPU contains an Arithmetic and Logic Unit, ALU
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Machine Language instruction set
Instruction Explanation ADD ACC ACC + (A) SUB ACC ACC - (A) LOAD ACC (A) STORE (A) (ACC) BRANCH BRANCH to A COND BRANCH if ACC = 0 BRANCH to A
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Registers CSIAR(Control Storage Instruction Address Register) points to the next microinstruction to be executed. MIR(Microinstruction Register): contains the current microinstruction being executed. PSIAR(Primary Storage Instruction Address Register) primary storage address of the next machine language instruction to be interpreted. SAR(Storage Address Register) the address of the location in primary storage being accessed. SDR(Storage Data Register) holds the data TMPR(Temporary Register) the address portion of the machine instruction in the SDR so that it can be placed in the SAR
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Micro Operations Register transfers (REG is ACC, PSIAR, or TMPR): SDR <-- REG REG <-- SDR SAR <-- REG Primary storage operations: READ WRITE Sequencing operations: CSIAR <-- CSIAR + 1 CSIAR <-- decoded SDR CSIAR <-- constant SKIP (add 2 to CSIAR if ACC = 0; else add 1) Operations involving the accumulator: ACC <-- ACC + REG ACC <-- ACC - REG ACC <-- REG REG <-- ACC ACC <-- REG + 1
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Primary Storage Control Storage SDR 1 2 10 11 12 13 14 15 16 17 18 19
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... TMPR MIR 76 10 50 PSIAR (ADD 50) SAR ADD ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 1 2 10 11 12 13 14 15 16 17 18 19
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... TMPR MIR 76 10 50 PSIAR (ADD 50) 76 SAR ADD ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 1 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... TMPR MIR 76 10 50 PSIAR (ADD 50) 76 SAR ADD ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 2 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... TMPR MIR 76 10 50 PSIAR (ADD 50) 76 SAR ADD ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 10 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... TMPR MIR 76 10 50 PSIAR (ADD 50) 76 SAR ADD ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 10 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... (ACC) TMPR MIR 76 10 50 PSIAR (ADD 50) 76 SAR ADD ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 11 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... (ACC) TMPR MIR 76 10 50 PSIAR (ADD 50) 76 SAR ADD 77 ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 12 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... (ACC) TMPR MIR 77 10 50 PSIAR (ADD 50) 76 SAR ADD 77 ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 13 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... (ACC) TMPR MIR 77 10 50 PSIAR (ADD 50) 76 SAR ADD (ACC) ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 14 1 2 10 11 12 13 14 15 16 17 18
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... 50 TMPR MIR 77 10 50 PSIAR (ADD 50) 76 SAR ADD (ACC) ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 80 50 15 1 2 10 11 12 13 14 15 16
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 Fetch CSIAR 74 75 76 77 78 79 .... 50 TMPR MIR 77 10 50 PSIAR (ADD 50) 50 SAR ADD (ACC) ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 80 50 16 1 2 10 11 12 13 14 15 16
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 80 Fetch CSIAR 74 75 76 77 78 79 .... 50 TMPR MIR 77 10 50 PSIAR (ADD 50) 50 SAR ADD (ACC) ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 80 50 17 1 2 10 11 12 13 14 15 16
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 80 Fetch CSIAR 74 75 76 77 78 79 .... 80 TMPR MIR 77 10 50 PSIAR (ADD 50) 50 SAR ADD (ACC) ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 80 50 18 1 2 10 11 12 13 14 15 16
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 80 Fetch CSIAR 74 75 76 77 78 79 .... 80 TMPR MIR 77 10 50 PSIAR (ADD 50) 50 SAR ADD (ACC)+80 ACC Primary Storage Control Storage
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Primary Storage Control Storage SDR 80 50 1 2 10 11 12 13 14 15 16 17
1 2 10 11 12 13 14 15 16 17 18 19 20 21 SAR <-- PSIAR READ CSIAR <-- decode SDR TMPR <-- ACC ACC <-- PSIAR + 1 PSIAR <-- ACC ACC <-- TMPR TMPR <-- SDR SAR <-- TMPR ACC <-- ACC + TMPR CSIAR <-- 0 80 Fetch CSIAR 74 75 76 77 78 79 .... 80 TMPR MIR 77 10 50 PSIAR (ADD 50) 50 SAR ADD (ACC)+80 ACC Primary Storage Control Storage
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