Figure 10–1 A 64-cell memory array organized in three different ways.

Name: Figure 10–1 A 64-cell memory array organized in three different ways.
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Description: Figure 10–1 A 64-cell memory array organized in three different ways.

Figure 10–1 A 64-cell memory array organized in three different ways.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–2 Examples of memory address in a 2-dimensional array.

Figure 10–3 Example of memory address in a 3-dimensional array.

Figure 10– Block diagram of a 2-dimensional memory and a 3-dimensional memory showing address bus, address decoder(s), bidirectional data bus, and read/write inputs. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–5 Illustration of the write operation.

Figure 10–6 Illustration of the read operation.

Figure 10–7 The RAM family. Thomas L. Floyd Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–8 A typical SRAM latch memory cell.

Figure 10–9 Basic SRAM array.

Figure 10–10 Logic diagram for an asynchronous 32k x 8 SRAM.

Figure 10–11 Basic organization of an asynchronous 32k x 8 SRAM.

Figure 10–12 Basic read and write cycle timing for the SRAM in Figure 10–11.

Figure 10–13 A basic block diagram of a synchronous SRAM with burst feature.

Figure 10–14 Address burst logic.

Figure 10–15 Block diagram showing L1 and L2 cache memories in a computer system.

Figure 10–16 A MOS DRAM cell. Thomas L. Floyd Digital Fundamentals, 9e

Figure 10–17 Basic operation of a DRAM cell.

Figure 10–18 Simplified block diagram of a 1M x 1 DRAM.

Figure 10–19 Basic timing for address multiplexing.

Figure 10–20 Normal read and write cycle timing.

Figure 10–21 Fast page mode timing for a read operation.

Figure 10–22 The ROM family. Thomas L. Floyd Digital Fundamentals, 9e

Figure 10–23 ROM cells. Thomas L. Floyd Digital Fundamentals, 9e

Figure 10–24 A representation of a 16 x 8-bit ROM array.

Figure 10–25 Representation of a ROM programmed as a binary-to-Gray code converter.

Figure 10–26 A 256 x 4 ROM logic symbol
Figure 10– A 256 x 4 ROM logic symbol. The A designator means that the 8-bit address code selects addresses 0 through 255. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–27 A 1024-bit ROM with a 256 x 4 organization based on a 32 x 32 array.

Figure 10– ROM access time (ta) from address change to data output with chip enable already active. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–29 MOS PROM array with fusible links
Figure 10– MOS PROM array with fusible links. (All drains are commonly connected to VDD.) Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–30 Ultraviolet erasable PROM package.

Figure 10–31 The logic symbol for a 2048 x 8 UV EPROM.

Figure 10– Timing diagram for a 2048 x 8 UV EPROM programming cycle, with critical setup times (ts) and hold times (th) indicated. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–33 The storage cell in a flash memory.

Figure 10– Simplified illustration of storing a 0 or a 1 in a flash cell during the programming operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–35 The read operation of a flash cell in an array.

Figure 10–36 Simplified illustration of removing charge from a cell during erase.

Figure 10–37 Basic flash memory array.

Figure 10– Expansion of two 65,536 x 4 ROMs into a 65,536 x 8 ROM to illustrate word-length expansion. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–39 A 64k x 4 ROM. Thomas L. Floyd Digital Fundamentals, 9e

Figure 10–40 Thomas L. Floyd Digital Fundamentals, 9e

Figure 10–42 Illustration of word-length expansion with two 2m x n RAMs forming a 2m x 2n RAM.

Figure 10–44 Illustration of word-capacity expansion.

Figure 10–46 30-pin and 72-pin SIMMs.

Figure 10–47 A SIMM/DIMM is inserted into a socket on a system board.

Figure 10–48 Comparison of conventional and FIFO register operation.

Figure 10–49 Block diagram of a typical FIFO serial memory.

Figure 10–50 Examples of the FIFO register in data-rate buffering applications.

Figure 10–51 Register stack.

Figure 10–52 Simplified illustration of pushing data onto the stack.

Figure 10–53 Simplified illustration of pulling data from the stack.

Figure 10–54 Representation of a 64 kB memory with the 16-bit addresses expressed in hexadecimal.

Figure 10–55 Illustration of the PUSH operation for a RAM stack.

Figure 10–56 Illustration of the POP operation for the RAM stack.

Figure 10–57 A CCD (charge-coupled device) channel.

Figure 10–58 A hard disk drive.

Figure 10–59 Simplified read/write head operation.

Figure 10–60 Hard disk organization and formatting.

Figure 10–61 The 3.5 inch floppy disk (diskette).

Figure 10–62 QIC tape. Thomas L. Floyd Digital Fundamentals, 9e

Figure 10–63 Basic principle of a magneto-optical disk.

Figure 10–64 Basic operation of reading data from a CD-ROM.

Figure 10–65 Block diagram for a complete contents check of a ROM.

Figure 10–66 Flowchart for a complete contents check of a ROM.

Figure 10– Simplified illustration of a programmed ROM with the checksum stored at a designated address. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 10–68 Flowchart for a basic checksum test.

Figure 10–69 The RAM checkerboard test pattern.

Figure 10–70 Flowchart for basic RAM checkerboard test.

Figure 10–71 Block diagram of the complete security system.

Figure 10–72 Block diagram of the memory logic.

Figure 10–73 Memory cell logic.

Figure 10–74 The memory address decoder.

Figure 10–75 Memory array and address decoder.

Figure 10–76 Illustration of entering a security code (4739) into the memory.

Figure 10–77 The complete memory logic.

Figure 10–78 The security code logic (from Chapter 11).

Figure 10–79 The complete security system.

Figure 10–1 A 64-cell memory array organized in three different ways.

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Figure 10–1 A 64-cell memory array organized in three different ways.

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