1. Execution Cycle

2. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 1 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

3. MIPS Microarchitecture Recall the datapath for the lw (load word) command 2

4. MIPS Microarchitecture The first step was to fetch the instruction 3

5. MIPS Microarchitecture fetch the instruction 4

6. MIPS Microarchitecture The next step was to decode the instruction 5

7. MIPS Microarchitecture decode the instruction 6

8. MIPS Microarchitecture Next, execute the instruction 7

9. MIPS Microarchitecture execute the instruction 8

10. MIPS Microarchitecture Next, access memory (if necessary) 9

11. MIPS Microarchitecture Finally, write back to a register 10

12. MIPS Microarchitecture write back to a register 11

13. MIPS Microarchitecture Just described classic 5-stage execution cycle Fetch Decode Execute Memory Write Back 5-stage execution cycle typical of RISC machines RISC is easier to explain CISC is more complicated… x86 is CISC 12

14. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 13 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

15. Execution Cycle (aka Instruction Cycle) 14 IF – Instruction Fetch ID – Instruction Decode EX - Execute MEM – Memory WB- Write Back

16. Execution Cycle - Fetch 15 IF ID EXE MEM WB Send the program counter (PC) to memory fetch the current instruction from memory Update the PC PC = PC + 4 (since each instruction is four bytes)

17. Execution Cycle - Decode 16 IF ID EXE MEM WB Figure out type of instruction (e.g., load, add, etc.) Based on “opcode” Determine registers involved aka “operands” Get things “setup” for execution Control Unit sets appropriate pins

18. Execution Cycle - Execute 17 IF ID EXE MEM WB ALU operates on operands prepared during decode ALU performs function based on instruction type Arithmetic (add, subtract, …) Logic (equivalence, negation, …)

19. Execution Cycle - Memory 18 IF ID EXE MEM WB If instruction is LOAD, Read data from effective memory address Effective memory address computed during EXE If instruction is STORE, Write data from register to effective memory address Effective memory address computed during EXE MEM is an OPTIONAL execution stage Memory access does not always occur

20. Execution Cycle – Write Back 19 IF ID EXE MEM WB Write results “back” to a register Result type depends on instruction Results could be from: ALU computation -or- Memory access (i.e., load)

21. Execution Cycle – Fetch The execution cycle then repeats… The next instruction is already indicated by PC Recall that PC set to PC + 4 during previous fetch 20 IF ID EXE MEM WB

22. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 21 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

23. Pipelining It’s laundry day, and you have to complete the following tasks: 1.Wash white clothes in washing machine 2.Dry white clothes in dryer 3.Wash color clothes in washing machine 4.Dry color clothes in dryer 5.Wash athletic clothes in washing machine 6.Dry athletic clothes in dryer 22

24. Pipelining Would you do the following? I.e., Wait for each load to wash and dry before starting next? 23 wash whites dry whites wash colors dry colors wash athletic dry athletic time

25. Pipelining Heck no!! What a waste of time!! What do you do instead? 24 wash whites dry whites wash colors dry colors wash athletic dry athletic time

26. Pipelining Overlap: wash one load while another is drying 25 wash whites dry whites wash colors dry colors wash athletic dry athletic time

27. Pipelining Do more things at once… 26 wash whites dry whites wash colors dry colors wash athletic dry athletic time

28. Pipelining Complete tasks in less time… 27 FREE TIME!!

29. Pipelining Can this be applied to the execution cycle? Yes!! Fetch the next instruction while decoding the current instruction? Decode the next instruction while executing the current instruction? … 28 IF ID EX MEM WB IF ID EX MEM WB

30. Pipelining Typical 5-stage pipeline of RISC CPU 5 th instruction is being fetched while 1 st instruction is being written back There are much deeper and fancier pipelines… 29 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

31. Pipelining Typical 5-stage pipeline of RISC CPU 9 clock cycles to complete 5 instructions 30 clock cycle Instruction123456789 instr-1IFID EX E MEMWB instr-2IFIDEXEMEMWB instr-3IFIDEXEMEMWB instr-4IFIDEXEMEMWB instr-5IFIDEXEMEMWB

32. Pipelining Without pipelining 25 clock cycles to complete 5 instructions 31 IF ID EX MEM WB IF ID EX MEM WB … …

33. Pipelining There are several things that can disrupt a pipeline Called hazards E.g., What happens if the next instruction depends on the result of the current instruction? 32

34. Pipeline Hazards Three types of hazards Control hazard Data hazard Structural hazard 33

35. Pipeline Hazards: Control Control Hazard Occurs when pipelining branches (e.g., if statements) … or other instructions that change the PC 34 ???

36. Pipeline Hazards: Data Data Hazard Occurs when an instruction tries to use data before it’s available For example: 1: R1 <- R2 + R3 2: R4 <- R1 + R5 Contents in R1 (register 1) may have been loaded for instruction #2 before instruction #1 has finished. Several types of data hazards… 35

37. Pipeline Hazards: Data Data Hazard 1: R1 <- R2 + R3 2: R4 <- R1 + R5 36 IF ID EX MEM WB IF ID EX MEM WB 1: 2: R1 used in instruction #2’s execution before instruction #1 writes back

38. Pipeline Hazards: Structural Structural Hazard Occurs when one hardware component is needed by two (pipelined) tasks at same time Example: read from and write to memory at the same time Fetch an instruction from memory while writing data to memory Hence why instruction and data memory are separated 37

39. Pipelining: Solutions Ways to minimize pipeline hazards Stall Flush Out-of-order execution Forwarding Bypassing Branch prediction … Beyond the scope of this course… Learn about / master pipeline hazards 38

40. Break Time!!! 39 I don’t fish, but this likes nice…

41. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 40 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

42. Big vs. Little Endian Some important jargon: 0x97 46 AB 07 1001 0111 0100 0110 1010 1011 0000 0111 41 MSB: Most Significant Bit LSB: Least Significant Bit

43. Big vs. Little Endian 0x97 46 AB 07 1001 0111 0100 0110 1010 1011 0000 0111 42 Most Significant Byte Least Significant Byte MSB can stand for most significant bit OR byte LSB can stand for least significant bit OR byte

44. Big vs. Little Endian Endian refers to the ordering of bytes for multiple byte words How the bytes are stored in memory How the bytes are interpreted Whether the MSB comes “first” or “last” Whether the LSB comes “first” or “last” 43 MSB - Most Significant Byte LSB - Least Significant Byte

45. Big Endian Most significant byte stored at smallest address Least significant byte stored at largest address 0x97 46 AB 07 44

46. Little Endian Most significant byte stored at largest address Least significant byte stored at smallest address 0x97 46 AB 07 45

47. Example Store 0x46 A0 B7 FF using: 46 Big EndianLittle Endian

48. Example Store 0x46 A0 B7 FF using: 47 Big EndianLittle Endian

49. Outline (Brief) Review of MIPS Microarchitecture Execution Cycle Pipelining Big vs. Little Endian-ness CPU Execution Time 48 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

50. CPU Execution Time 49

51. Example What is the execution time required to complete: 10 instructions with 5 cycles per instruction using a 100 Hz CPU? Hz = cycles / second 50

52. Example 51 10 instructions 5 cycles per instruction 100 Hz CPU = 100 cycles per second = 1 second per 100 cycles

53. Next Time.. Review for midterm Bring your laptop (if you can) Linux bootstrap day Install VMWare onto your computer Will need very soon!! 52