1. 12-1 EE 319K Introduction to Embedded Systems Lecture 12: Serial Communication (UART), Lab 9, FIFO Queues Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

2. 12-2 Agenda  Recap  ADC, fixed-point  Assembly-C mix  Lab 8  Agenda  Communication  Serial: UART, interrupts  FIFO Queues used as buffers in communication  Lab 9: Distributing Lab 8 oTransmitter uses ADC to read potentiometer oReceiver uses LCD to display position. oFIFO serves as buffer at receiver Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

3. 12-3 Universal Asynchronous Receiver/Transmitter (UART)  UART (Serial Port) Interface  Send/receive a frame of (5-8) data bits with a single (start) bit prefix and a 1 or 2 (stop) bit suffix  Baud rate is total number of bits per unit time oBaudrate = 1 / bit-time  Bandwidth is data per unit time oBandwidth = (data-bits / frame-bits) * baudrate Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

4. 12-4 TM4C123 LaunchPad I/O Pins

5. 12-5 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi RS-232 Serial Port // this U1Tx PD3 not connected // this U1Rx PD2 tied to U1Tx PD3 of other microcontroller 0

6. 12-6 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Serial I/O  Serial communication  Transmit Data (TxD), Receive Data (RxD), and Signal Ground (SG) implement duplex communication link  Both communicating devices must operate at the same bit rate  Least significant bit sent first Full duplex Half duplex Simplex

7. 12-7 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART - Transmitter

8. 12-8 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART - Transmitter  Tx Operation  Data written to UART0_DR_R opasses through 16-element FIFO opermits small amount of data rate matching between processor and UART  Shift clock is generated from 16x clock opermits differences in Tx and Rx clocks to be reconciled

9. 12-9 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART - Receiver

10. 12-10 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART - Receiver  Rx Operation  RXFE is 0 when data are available  RXFF is 1 when FIFO is full  FIFO entries have four control bits oBE set when Tx signal held low for more than one frame (break) oOE set when FIFO is full and new frame has arrived oPE set if frame parity error oFE set if stop bit timing error

11. 12-11 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART – Overrun Error 17 frames transmitted and none read => overrun error

12. 12-12 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi TM4C UART0 – Registers

13. 12-13 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi TM4C UART Setup  UART0 operation  UART clock started in SYSCTL_RCGCUART_R  Digital port clock started in SYSCTL_RCGCGPIO_R  UART0_CTL_R contains UART enable (UARTEN), Tx (TXE), and Rx enable (RXE) oset each to 1 to enable oUART disabled during initialization  UART0_IBRD_R and UART_FBRD_R specify baud rate obit rate = (bus clock frequency)/(16*divider) oex: want 19.2 kb/s and bus clock is 8 MHz o8 MHz/(16*19.2 k) = 26.04167 = 11010.000011 2 oTx and Rx clo ck rates must be within 5% to avoid errors  GPIO_PORTA_AFSEL_R to choose alternate function  Write appropriate values to GPIO_PORTA_PCTL_R (See slide 4)  GPIO_PORTA_DEN_R Enable digital I/O on pins 1-0  GPIO_PORTA_AMSEL_R no Analog I/O on pins 1-0  write to UART0_LCRH_R to activate

14. 12-14 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART Setup // Assumes a 50 MHz bus clock, creates 115200 baud rate void UART_Init(void){ SYSCTL_RCGCUART_R |= 0x0001; // activate UART0 SYSCTL_RCGCGPIO_R |= 0x0001; // activate port A UART0_CTL_R &= ~0x0001; // disable UART UART0_IBRD_R = 27; // IBRD=int(50000000/(16*115,200)) = int(27.1267) UART0_FBRD_R = 8; // FBRD = round(0.1267 * 64) = 8 UART0_LCRH_R = 0x0070; // 8-bit length, enable FIFO UART0_CTL_R = 0x0301; // enable RXE, TXE and UART GPIO_PORTA_AFSEL_R |= 0x03; // alt funct on PA1-0 GPIO_PORTA_PCTL_R = (GPIO_PORTA_PCTL_R&0xFFFFFF00)+0x00000011; GPIO_PORTA_DEN_R |= 0x03; // digital I/O on PA1-0 GPIO_PORTA_AMSEL_R &= ~0x03; // No analog on PA1-0 }

15. 12-15 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART Synchronization  Busy-wait operation

16. 12-16 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART Busy-Wait Send/Recv // Wait for new input, // then return ASCII code uint8_t UART_InChar(void) { while((UART0_FR_R&0x0010) != 0); // wait until RXFE is 0 return((uint8_t)(UART0_DR_R&0xFF)); } // Wait for buffer to be not full, // then output void UART_OutChar(uint8_t data) { while((UART0_FR_R&0x0020) != 0); // wait until TXFF is 0 UART0_DR_R = data; }

17. 12-17 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi UART Interrupts  UART0_IFLS_R register (bits 5,4,3) RXIFLSELRX FIFOSet RXRIS interrupt trigger when 0x0 ≥ ⅛ fullReceive FIFO goes from 1 to 2 characters 0x1 ≥ ¼ fullReceive FIFO goes from 3 to 4 characters 0x2 ≥ ½ fullReceive FIFO goes from 7 to 8 characters 0x3 ≥ ¾ fullReceive FIFO goes from 11 to 12 characters 0x4 ≥ ⅞ fullReceive FIFO goes from 13 to 14 characters TXIFLSELTX FIFOSet TXRIS interrupt trigger when 0x0 ≤ ⅞ empty Transmit FIFO goes from 15 to 14 characters 0x1 ≤ ¾ empty Transmit FIFO goes from 13 to 12 characters 0x2 ≤ ½ empty Transmit FIFO goes from 9 to 8 characters 0x3 ≤ ¼ empty Transmit FIFO goes from 5 to 4 characters 0x4 ≤ ⅛ empty Transmit FIFO goes from 3 to 2 characters

18. 12-18 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Lab 9 – Distributed Measurement Position Sensor Voltage 0 to +3.3V ADC hardware ADC driver Sample 0 to 4095 SysTick ISR Sample 0 to 4095 SysTick hardware LCD display LCD driver Fixed-point 0 to 3.000 Position 0 to 3 cm UART driver UART1 hardware main UART1 ISR UART1 hardware Computer 1 Computer 2 Message Message FIFO MessageMessage Message Message STX d1. d2 d3 d4 CR ETX Message

19. 12-19 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Lab9: Transmitter SysTick ISR  Toggle heartbeat  Sample ADC  Toggle heartbeat  Convert to integer part of fixed point  Send message, 8 calls to UART_OutChar  STX  Ones digit  Decimal point  Tenths digit  Hundreds digit  Thousandth digit  CR  ETX  Toggle heartbeat Busy-wait version

20. 12-20 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Lab9: UART Rx Interrupt  Interrupt Trigger, sets RXRIS  Receive FIFO has gone from 7 to 8 elements (1/2 full)  Initialization (add these)  Arm RXRIS UART1_IM_R |= 0x10;  Set UART1_IFLS_R bits 5,4,3 to 010 (1/2 full)  NVIC_PRI1_R // bits 21-23  NVIC_EN0_R // enable interrupt 6 in NVIC  Interrupt vector in startup.s  Name ISR UART1_Handler  Acknowledge (in ISR)  UART1_ICR_R = 0x10;

21. 12-21 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Lab9: Interrupt+Mailbox?  RXRIS ISR  Read UART1_DR_R  Store in RXmail  Set RXstatus  Main loop  Wait for RXstatus  Read RXmail  Clear RXstatus  Convert to distance  Display on LCD Background threadForeground thread Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi What can go wrong?

22. 12-22 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi First-In/First-Out (FIFO) Queues  Order preserving  Producer(s) put (on tail end)  Consumer(s) get (from head end)  Buffer decouples producer & consumer  Even out temporary mismatch in rates

23. 12-23 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Operation  I/O bound input interface

24. 12-24 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Operation  High bandwidth input burst

25. 12-25 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Queue Synchronization Lab 9

26. 12-26 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Lab 9 - RXRIS ISR 1.toggle PF2 (change from 0 to 1, or from 1 to 0), heartbeat 2.toggle PF2 (change from 0 to 1, or from 1 to 0), heartbeat 3.as long as the RXFE bit in the UART1_FR_R is zero oRead bytes from UART1_DR_R oPut all bytes into your software FIFO, RxFifo_Put oShould be exactly 8 bytes, but could be more possibly oIf your software FIFO is full (data lost) increment a global error count (but don’t loop back) oThe message will be interpreted in the main program 4.Increment a Counter, odebugging monitor of the number of UART messages received 5.acknowledge the interrupt by clearing the flag which requested it oUART1_ICR_R = 0x10; // clears bit 4 (RXRIS) in RIS register 6.toggle PF2 (change from 0 to 1, or from 1 to 0), heartbeat 7.return from interrupt

27. 12-27 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Queue Implementation  How is memory allocated?  FIFO implies that we write new data at the head of the queue and we read data from the tail of the queue  What problem does this cause?  To address that problem the queue is operated in a circular manner  An array of locations is processed so that the FIRST element of array appears to follow the LAST element of the array

28. 12-28 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Queue Implementation  Two parameters are needed to specify the FIFO buffer (array)  FIRST (usually index 0) opoints to the first location of the buffer  LIMIT (usually index SIZE) opoints to last location+1 of the buffer osince LIMIT is outside the buffer, data must not be written there  FIRST and LIMIT are constants othey are NOT modified by either the source or sink processing routines

29. 12-29 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Queue Implementation  PutPt: Points to the location where the next element to be added goes  GetPt: Points to the location of the oldest valid element, hence the element to be removed first

30. 12-30 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Full/Empty Conditions  FIFO Parameter Relations  Buffer is EMPTY oPutPt equals GetPt  Buffer is FULL oPutPt + 1 equals GetPt  note that there is no data stored at PutPt  as a result, if N locations are allocated for a buffer, only N-1 data elements will fill the buffer

31. 12-31 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Wrapping Pointer wrap on 2nd put Pointer wrap on 4th get FIRST LIMIT FIRST LIMIT

32. 12-32 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Queue  FIFO Implementations  FIFO_Put ostores a single value on the FIFO queue  operates with interrupts disabled  updates PutPt detects buffer full condition  handles transition from LIMIT-1 to FIRST  FIFO_Get oreads a single value from the FIFO queue  operates with interrupts disabled  updates GetPt detects buffer empty condition  handles transition from LIMIT-1 to FIRST

33. 12-33 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO in C #define FIFO_SIZE 10 int32_t static *PutPt; int32_t static *GetPt; int32_t static Fifo[FIFO_SIZE]; void Fifo_Init(void){ PutPt = GetPt = &Fifo[0]; } static means private to this file

34. 12-34 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Routines in C int Fifo_Put(int32_t data) { int32_t *tempPt; tempPt = PutPt+1; // see if there is room if(tempPt==&Fifo[FIFO_SIZE]){ tempPt = &Fifo[0]; } if(tempPt == GetPt){ return(0); // full! } else{ *(PutPt) = data; // save PutPt = tempPt; // OK return(1); } Actually plus 4 bytes

35. 12-35 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Routines in C int Fifo_Get(int32_t *datapt){ if(PutPt == GetPt){ return(0); // Empty } else{ *datapt = *(GetPt++); if(GetPt==&Fifo[FIFO_SIZE]){ GetPt = &Fifo[0]; } return(1); } Actually plus 4 bytes

36. 12-36 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Queue – Index Implementation  FIFO Implementations  FIFO_Put ostores a single value on the FIFO queue  operates with interrupts disabled  updates PutI detects buffer full condition  handles transition from LIMIT-1 to FIRST  FIFO_Get oreads a single value from the FIFO queue  operates with interrupts disabled  updates GetI detects buffer empty condition  handles transition from LIMIT-1 to FIRST

37. 12-37 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO in C – Index Implementation #define FIFO_SIZE 10 int32_t static PutI; //Index in FIFO to // put new item in int32_t static GetI; //Index of oldest // item in FIFO int32_t static Fifo[FIFO_SIZE]; void Fifo_Init(void){ PutI = GetI = 0; } static means private to this file

38. 12-38 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO in C – Index Implementation int Fifo_Put(int32_t data) { if ( (PutI+1)% FIFO_SIZE) == GetI) { return(0); } FIFO[PutI] = data; PutI = (PutI+1)%FIFO_SIZE; return(1); } int Fifo_Get(int32_t *datapt) { if (GetI == PutI) { return(0); } *datapt = FIFO[GetI]; GetI = (GetI+1)%FIFO_SIZE; return(1); } Empty FIFO check Full FIFO check

39. 12-39 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi FIFO Full Errors Average producer rate exceeds the average consumer rate  Sample ADC every 50 ms  Average time to process the sample is 51 ms  Solution: decrease producer rate or increase consumer rate oLower sampling rate oFaster computer oMore efficient compiler oRewrite time-critical code in assembly oMore computers (distributed processing) Producer rate temporarily exceeds the consumer rate  Sample ADC every 50 ms  Every 100th sample it takes 1 sec to process  Solution: increase FIFO queue size