1. Unit 12 Registers and Counters Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2. 22004/05/20Registers and Counters Outline 12.1Registers and Register Transfers 12.2Shift Registers 12.3Design of Binary Counters 12.4Counters for Other Sequences 12.5Counter Design Using S-R and J-K Flip-Flops Flip-Flops 12.6Derivation of Flip-Flop Input Equations -- Summary -- Summary

3. 32004/05/20Registers and Counters S-R Flip-Flop Inputs

4. 42004/05/20Registers and Counters S-R Flip-Flop Inputs

5. 52004/05/20Registers and Counters Next-State Table

6. 62004/05/20Registers and Counters Counter Using S-R Flip-Flops

7. 72004/05/20Registers and Counters Counter Using S-R Flip-Flops

8. 82004/05/20Registers and Counters Counter Using J-K Flip-Flops

9. 92004/05/20Registers and Counters Counter Using J-K Flip-Flops

10. 102004/05/20Registers and Counters Counter Using J-K Flip-Flops

11. 112004/05/20Registers and Counters Counter Using J-K Flip-Flops

12. 122004/05/20Registers and Counters Outline 12.1Registers and Register Transfers 12.2Shift Registers 12.3Design of Binary Counters 12.4Counters for Other Sequences 12.5Counter Design Using S-R and J-K Flip-Flops Flip-Flops 12.6Derivation of Flip-Flop Input Equations -- Summary -- Summary

13. 132004/05/20Registers and Counters Flip-Flop Input Equations

14. 142004/05/20Registers and Counters Flip-Flop Input Equations

15. 152004/05/20Registers and Counters Homework #5 1.12.1 2.12.2 3.12.3 4.12.4 5.12.5 6.12.6 7.12.7 8.12.8 9.12.9 Paper Submission, due on June 3, 2004. Late submission will not be accepted.