1. EDA Lab. Dept. of Computer Engineering C. N. U. 1 FSM Structures Mealy, Moore and Combined Mealy/Moore outputs Figure 8.3

2. EDA Lab. Dept. of Computer Engineering C. N. U. 2

3. 3 Bad FSM Model State Diagram

4. EDA Lab. Dept. of Computer Engineering C. N. U. 4 VHDL Code

5. EDA Lab. Dept. of Computer Engineering C. N. U. 5 Contd

6. EDA Lab. Dept. of Computer Engineering C. N. U. 6 Problems of FSM1 – BAD 1.no reset, no next state value defined for the unused state. –2bits FFs: 3 states used, one unused state. 2.Read and Write output assignment infer extra two FFs. –To avoid extra FFs, use separate combinational process. 3.variable initialization –Ignored by the synthesis tools.

7. EDA Lab. Dept. of Computer Engineering C. N. U. 7 FSM1_GOOD

8. EDA Lab. Dept. of Computer Engineering C. N. U. 8

9. 9 Synthesized Circuit

10. EDA Lab. Dept. of Computer Engineering C. N. U. 10 FSM 2 State Diagram

11. EDA Lab. Dept. of Computer Engineering C. N. U. 11 VHDL Code (Bad)

12. EDA Lab. Dept. of Computer Engineering C. N. U. 12 Contd Output Y –Assigned under clockevent … statement. –Extra FFs are inferred.

13. EDA Lab. Dept. of Computer Engineering C. N. U. 13 Good Model 1 (1 sequential process, 1 combination process, selected signal assignment for Y)

14. EDA Lab. Dept. of Computer Engineering C. N. U. 14 Contd

15. EDA Lab. Dept. of Computer Engineering C. N. U. 15 Sequential process & Combinational process Sequential process –Description with respect to the edge point –Input sampled just before the edge –Output Combinational process inputoutput inputoutput

16. EDA Lab. Dept. of Computer Engineering C. N. U. 16 FSM 2_GOOD2 Combined current state and next state logic Separate output logic

17. EDA Lab. Dept. of Computer Engineering C. N. U. 17 Separate output logic

18. EDA Lab. Dept. of Computer Engineering C. N. U. 18 Contd

19. EDA Lab. Dept. of Computer Engineering C. N. U. 19 Synthesized Circuit

20. EDA Lab. Dept. of Computer Engineering C. N. U. 20 FSM 2_GOOD3 Combined next state and output logic Separate current state logic

21. EDA Lab. Dept. of Computer Engineering C. N. U. 21 VHDL Code

22. EDA Lab. Dept. of Computer Engineering C. N. U. 22

23. EDA Lab. Dept. of Computer Engineering C. N. U. 23 FSM 2_GOOD4 Combined current state, next state and output logic

24. EDA Lab. Dept. of Computer Engineering C. N. U. 24 VHDL Code

25. EDA Lab. Dept. of Computer Engineering C. N. U. 25

26. EDA Lab. Dept. of Computer Engineering C. N. U. 26 Car Speed Controller FSM State Diagram

27. EDA Lab. Dept. of Computer Engineering C. N. U. 27 Input primary branch directives

28. EDA Lab. Dept. of Computer Engineering C. N. U. 28

29. EDA Lab. Dept. of Computer Engineering C. N. U. 29 State value primary branch directives

30. EDA Lab. Dept. of Computer Engineering C. N. U. 30

31. EDA Lab. Dept. of Computer Engineering C. N. U. 31 Contd

32. EDA Lab. Dept. of Computer Engineering C. N. U. 32 Angular Position FSM using Gray and Johnson state encoding State Diagram

33. EDA Lab. Dept. of Computer Engineering C. N. U. 33 Contd Input –Physical Position: asynchronous input(loaded when reset = 1) –MOVE CW: 45˚ clock wise move –MOVE CCW: 45˚ counter clock wise move Two ways of representing state encoding 1.Use a signal of an enumerated type for which a single synthesis specific attribute is applied. Attribute name is specific to the synthesis tool, not portable, needs to be changed.

34. EDA Lab. Dept. of Computer Engineering C. N. U. 34 VHDL Code

35. EDA Lab. Dept. of Computer Engineering C. N. U. 35 Contd 2. Use constants to represent the individual state values. It is directly portable to other synthesis tools.

36. EDA Lab. Dept. of Computer Engineering C. N. U. 36

37. EDA Lab. Dept. of Computer Engineering C. N. U. 37 Angular position FSM

38. EDA Lab. Dept. of Computer Engineering C. N. U. 38 Contd

39. EDA Lab. Dept. of Computer Engineering C. N. U. 39 Contd

40. EDA Lab. Dept. of Computer Engineering C. N. U. 40 Contd

41. EDA Lab. Dept. of Computer Engineering C. N. U. 41 Contd

42. EDA Lab. Dept. of Computer Engineering C. N. U. 42 Black Jack Game Machine Blackjack Game –Blackjack is the most popular of the card games played at the tables in casinos. It is played with a standard deck of 52 cards. The four suits; spades, hearts, diamonds and clubs have no significance and are ignored. The Jack, Queen and King all have a value of 10. The ace is the most powerful card having a value of 1 or 11 depending upon what the player chooses. –Blackjack is also known as pontoon or 21 because 21 is the highest rated total card value a player can hold. Blackjack is the name given to the strongest hand consisting of an ace and a 10 valued card. –The object of the game is to beat the dealer. The dealer has no object other than to follow the rules of the casino, which is to stand(hold) on hands of 17 or more, and to draw another card on hands of 16 or less. –A player looses if his or her total card value is less than the dealers total, or, he or she has over 21 and so has bust. If a player wants to improve his hand he can ask the dealer for another card. This is called drawing or hitting. If satisfied with the total card value he can stand(hold).

43. EDA Lab. Dept. of Computer Engineering C. N. U. 43

44. EDA Lab. Dept. of Computer Engineering C. N. U. 44

45. EDA Lab. Dept. of Computer Engineering C. N. U. 45

46. EDA Lab. Dept. of Computer Engineering C. N. U. 46 VHDL package defining four enumerated state encoding data types

47. EDA Lab. Dept. of Computer Engineering C. N. U. 47

48. EDA Lab. Dept. of Computer Engineering C. N. U. 48 FSM with selectable state encoding – Blackjack game machine

49. EDA Lab. Dept. of Computer Engineering C. N. U. 49 Contd

50. EDA Lab. Dept. of Computer Engineering C. N. U. 50 Contd

51. EDA Lab. Dept. of Computer Engineering C. N. U. 51 Contd

52. EDA Lab. Dept. of Computer Engineering C. N. U. 52 Contd

53. EDA Lab. Dept. of Computer Engineering C. N. U. 53 Contd

54. EDA Lab. Dept. of Computer Engineering C. N. U. 54 Contd

55. EDA Lab. Dept. of Computer Engineering C. N. U. 55 Contd

56. EDA Lab. Dept. of Computer Engineering C. N. U. 56 Contd

57. EDA Lab. Dept. of Computer Engineering C. N. U. 57 Contd

58. EDA Lab. Dept. of Computer Engineering C. N. U. 58 Contd

59. EDA Lab. Dept. of Computer Engineering C. N. U. 59 Contd

60. EDA Lab. Dept. of Computer Engineering C. N. U. 60 Contd

61. EDA Lab. Dept. of Computer Engineering C. N. U. 61 FSMs with a Mealy or Moore output State Diagram for FSMs with a Mealy and Moore output

62. EDA Lab. Dept. of Computer Engineering C. N. U. 62

63. EDA Lab. Dept. of Computer Engineering C. N. U. 63 FSM modeled with NewColor as a Mealy type output

64. EDA Lab. Dept. of Computer Engineering C. N. U. 64 Contd

65. EDA Lab. Dept. of Computer Engineering C. N. U. 65 Contd

66. EDA Lab. Dept. of Computer Engineering C. N. U. 66 Contd

67. EDA Lab. Dept. of Computer Engineering C. N. U. 67 FSM modeled with NewColor as a Moore type output

68. EDA Lab. Dept. of Computer Engineering C. N. U. 68 Contd

69. EDA Lab. Dept. of Computer Engineering C. N. U. 69 Contd

70. EDA Lab. Dept. of Computer Engineering C. N. U. 70 FSM modeled with a Mealy and a Moore Output

71. EDA Lab. Dept. of Computer Engineering C. N. U. 71 Contd

72. EDA Lab. Dept. of Computer Engineering C. N. U. 72 Contd

73. EDA Lab. Dept. of Computer Engineering C. N. U. 73 Contd Moore Output –Dependent only on the current state, early output.

74. EDA Lab. Dept. of Computer Engineering C. N. U. 74 FSM with sequential next state logic Extra FF in the next state logic. State Diagram –BeenlnState3B (extra FF)

75. EDA Lab. Dept. of Computer Engineering C. N. U. 75

76. EDA Lab. Dept. of Computer Engineering C. N. U. 76 FSM with sequential next state logic

77. EDA Lab. Dept. of Computer Engineering C. N. U. 77 Contd

78. EDA Lab. Dept. of Computer Engineering C. N. U. 78 Contd

79. EDA Lab. Dept. of Computer Engineering C. N. U. 79 Contd

80. EDA Lab. Dept. of Computer Engineering C. N. U. 80 Contd Inferred FSM Structure with an additional FF in the next state logic

81. EDA Lab. Dept. of Computer Engineering C. N. U. 81 FSM with sequential output logic –State machine with an embedded counter Counter: parts of the state machines output logic. –State diagram implying sequential output logic

82. EDA Lab. Dept. of Computer Engineering C. N. U. 82 State diagram implying sequential output logic

83. EDA Lab. Dept. of Computer Engineering C. N. U. 83 FSM with sequential output logic

84. EDA Lab. Dept. of Computer Engineering C. N. U. 84 Contd

85. EDA Lab. Dept. of Computer Engineering C. N. U. 85 Contd Tried to use a synchronized value

86. EDA Lab. Dept. of Computer Engineering C. N. U. 86 Inferred FSM Structure with embedded counter

87. EDA Lab. Dept. of Computer Engineering C. N. U. 87 FSM with sequential next state and output logic - Blackjack Figure 8.12 State Diagram –VHDL coded with one single process statement.

88. EDA Lab. Dept. of Computer Engineering C. N. U. 88 VHDL Code

89. EDA Lab. Dept. of Computer Engineering C. N. U. 89 Contd

90. EDA Lab. Dept. of Computer Engineering C. N. U. 90 Contd

91. EDA Lab. Dept. of Computer Engineering C. N. U. 91 Contd

92. EDA Lab. Dept. of Computer Engineering C. N. U. 92 Contd

93. EDA Lab. Dept. of Computer Engineering C. N. U. 93 Contd

94. EDA Lab. Dept. of Computer Engineering C. N. U. 94 Contd

95. EDA Lab. Dept. of Computer Engineering C. N. U. 95 Interactive State Machine 1.Unidirectional

96. EDA Lab. Dept. of Computer Engineering C. N. U. 96

97. EDA Lab. Dept. of Computer Engineering C. N. U. 97 Interactive State Machine 2. Bidirectional

98. EDA Lab. Dept. of Computer Engineering C. N. U. 98

99. EDA Lab. Dept. of Computer Engineering C. N. U. 99 Unidirectional interactive FSMs Three different ways of controlling data path with unidirectional interactive FSMs

100. EDA Lab. Dept. of Computer Engineering C. N. U. 100

101. EDA Lab. Dept. of Computer Engineering C. N. U. 101 Data Path –Accepts three or four 4-bits values on the input. –Processes them, to provide sequences of either two or three, 9-bits values on the output. –Input data: A, B, C, D –Output data: Y1, Y2, Y3, (Y4) When ThreeOnly = 0 Y1 = A.B + A.C Y2 = A.D + B.C Y3 = B.D + C.D When ThreeOnly = 1 Y1 = A.B + A.C Y4 = B.C –Data Path controlled from Control Path 1, 2, 3

102. EDA Lab. Dept. of Computer Engineering C. N. U. 102

103. EDA Lab. Dept. of Computer Engineering C. N. U. 103 Control Path 1 Control Path –FSM master send Start FSM1, Start FSM2, Start FSM3 –FSM 1 Dedicated to provide four enable signals used to clock the serial input data into the appropriate holding register. –FSM 2 Send select signals which of the two held inputs to multiply together. Provide enable signals used to clock the multiplied result into the appropriate state register. –FSM 3 Simply provide the select lines used to select which result to output.

104. EDA Lab. Dept. of Computer Engineering C. N. U. 104 Contd Control Signals in control path 1

105. EDA Lab. Dept. of Computer Engineering C. N. U. 105 Contd Master FSM state diagram and FSM1, FSM2, FSM3 state diagram

106. EDA Lab. Dept. of Computer Engineering C. N. U. 106 Contd

107. EDA Lab. Dept. of Computer Engineering C. N. U. 107 Control Path 2 Three state diagram

108. EDA Lab. Dept. of Computer Engineering C. N. U. 108 Contd Control Path state diagram

109. EDA Lab. Dept. of Computer Engineering C. N. U. 109 1. Data path(VHDL Code)

110. EDA Lab. Dept. of Computer Engineering C. N. U. 110 Contd

111. EDA Lab. Dept. of Computer Engineering C. N. U. 111 Contd

112. EDA Lab. Dept. of Computer Engineering C. N. U. 112 Contd

113. EDA Lab. Dept. of Computer Engineering C. N. U. 113 2. Control Path 1 (VHDL Code)

114. EDA Lab. Dept. of Computer Engineering C. N. U. 114 Contd

115. EDA Lab. Dept. of Computer Engineering C. N. U. 115 Contd

116. EDA Lab. Dept. of Computer Engineering C. N. U. 116 Contd

117. EDA Lab. Dept. of Computer Engineering C. N. U. 117 Contd

118. EDA Lab. Dept. of Computer Engineering C. N. U. 118 Contd

119. EDA Lab. Dept. of Computer Engineering C. N. U. 119 Contd

120. EDA Lab. Dept. of Computer Engineering C. N. U. 120 Contd

121. EDA Lab. Dept. of Computer Engineering C. N. U. 121 Contd

122. EDA Lab. Dept. of Computer Engineering C. N. U. 122 Contd

123. EDA Lab. Dept. of Computer Engineering C. N. U. 123 Contd

124. EDA Lab. Dept. of Computer Engineering C. N. U. 124 Contd

125. EDA Lab. Dept. of Computer Engineering C. N. U. 125 Contd

126. EDA Lab. Dept. of Computer Engineering C. N. U. 126 3. Control Path 2 (VHDL Code)

127. EDA Lab. Dept. of Computer Engineering C. N. U. 127 Contd

128. EDA Lab. Dept. of Computer Engineering C. N. U. 128 Contd

129. EDA Lab. Dept. of Computer Engineering C. N. U. 129 Contd

130. EDA Lab. Dept. of Computer Engineering C. N. U. 130 Contd

131. EDA Lab. Dept. of Computer Engineering C. N. U. 131 Contd

132. EDA Lab. Dept. of Computer Engineering C. N. U. 132 Contd

133. EDA Lab. Dept. of Computer Engineering C. N. U. 133 Contd

134. EDA Lab. Dept. of Computer Engineering C. N. U. 134 Contd

135. EDA Lab. Dept. of Computer Engineering C. N. U. 135 Contd

136. EDA Lab. Dept. of Computer Engineering C. N. U. 136 4. Control Path 3 (VHDL Code)

137. EDA Lab. Dept. of Computer Engineering C. N. U. 137 Contd

138. EDA Lab. Dept. of Computer Engineering C. N. U. 138 Contd

139. EDA Lab. Dept. of Computer Engineering C. N. U. 139 Contd

140. EDA Lab. Dept. of Computer Engineering C. N. U. 140 Contd

141. EDA Lab. Dept. of Computer Engineering C. N. U. 141 Contd

142. EDA Lab. Dept. of Computer Engineering C. N. U. 142 Contd

143. EDA Lab. Dept. of Computer Engineering C. N. U. 143 Contd

144. EDA Lab. Dept. of Computer Engineering C. N. U. 144 Two Interactive FSM Controlling rotors –To control two mechanical interlocking rotors, which rotate in 90˚ increments in a clockwise or counter clockwise.

145. EDA Lab. Dept. of Computer Engineering C. N. U. 145

146. EDA Lab. Dept. of Computer Engineering C. N. U. 146 Contd Two Interactive FSM Controlling rotors –FSM1(FSM2) controls the rotor R1(R2) –Four states(Ang0, Ang90, Ang180, Ang270) –Inputs: CW-R1, CCW-R1, CW-R2, CCW-R2 –Two rotors should not be in the same position –Primary drive, Secondary drive Cannot be in or moved to some where if it is not occupied by the primary drive –R1_R2b = 1: R1 is drive R1_R2b = 0: R2 is drive

147. EDA Lab. Dept. of Computer Engineering C. N. U. 147

148. EDA Lab. Dept. of Computer Engineering C. N. U. 148 VHDL Code

149. EDA Lab. Dept. of Computer Engineering C. N. U. 149 Contd

150. EDA Lab. Dept. of Computer Engineering C. N. U. 150 Contd

151. EDA Lab. Dept. of Computer Engineering C. N. U. 151 Contd

152. EDA Lab. Dept. of Computer Engineering C. N. U. 152 Contd

153. EDA Lab. Dept. of Computer Engineering C. N. U. 153 Contd

154. EDA Lab. Dept. of Computer Engineering C. N. U. 154 Contd

155. EDA Lab. Dept. of Computer Engineering C. N. U. 155 Contd

156. EDA Lab. Dept. of Computer Engineering C. N. U. 156 Contd

157. EDA Lab. Dept. of Computer Engineering C. N. U. 157 Contd

158. EDA Lab. Dept. of Computer Engineering C. N. U. 158 Contd