1. a network of semiconductor technology Managing Light Products Must Have Products for Wireless, Battery Operated, and Optical Applications

2. Backlight Controllers Review LX1686LX1686 – Original Direct Drive CCFL Controller LX1688LX1688 –dedicated for Monitor Application LX1689LX1689 –wide range input dedicated for Portable Application

3. Feature & Benefits RangeMAX ® Technology – Direct Drive Digital Dimming Techniques Highest Efficiency Full brightness Control Smaller Form Factor Foolproof Lamp Strike Architecture

4. LX1686 Input voltage range 3.0V to 5.5V Standard Analog Dimming with DC voltage input Digital Dimming –with DC voltage input ( 100: 1) –with Digital PWM Input (100:1) On-chip Video Vertical Sync circuit for digital dimming Dimming Polarity Selection –Patented Direct Drive Fixed Frequency Topology –Digital Dimming with digital PWM Input –Patented Resonant lamp strike generation technique –Output Open Circuit Max. Voltage Regulation –Output Short Circuit Protection –Sleep Mode

5. LX1686 Key FeaturesKey Features –fixed frequency operation –wide digital dimming range –can lock to display video vertical frequency for zero-flicking during dimming –voltage limiting on step-up transformer secondary winding –transformer protection from over-heating during lamp strike –current regulation for consistent brightness over wider power supply input range –built in soft start feature –can operate with 3.0V power supply voltage –100mA output drive capability

6. LX 1686 Block Diagram

7. LX1686 Pin Description 1 PIN #PIN NAME Description 1AOUT Output driver A. 2 VSS_PPower ground for output drivers only. 3 VSSSignal ground. 4 AFD_CConnects to an external capacitor, C AFD. Forcing to ground or VDD will make the VCO oscillate at approximately 50% of the maximum VCO frequency. Forcing to VDD/2 will make the VCO oscillate at 2x the FVERT frequency. 5 RAMP_CConnects to external capacitor C RAMP for setting Direct Drive PWM operating frequency. 6 RAMP_RConnects to external resistor R RAMP for setting Direct Drive PWM operating frequency. 7 FVERTVertical frequency reference digital input. Has internal pull down. 8 PD_CRPhase Detector Filter. Part of phase lock loop. Connects to external capacitor and resistor network. 9 VCO_CConnects to external capacitor C VCO 10 BRT_POSBrightness control polarity. Has internal pull up. Leave open or pull up to VDD for dimming brightness proportional to BRITE voltage, connect to ground for brightness inversely proportional to BRITE voltage. 11 BRITEAnalog voltage input for brightness control.

8. LX1686 Pin Description 2 PIN #PIN NAME Description 12 DIG_DIMDigital Dimming Enable internal pull up. Leave open or pull up to VDD for operating in digital dimming mode. Connect to ground for analog dimming mode. 13 ENABLEChip Enable internal pull up. High enables the chip. Low disables. 14 I_RCurrent Reference Resistor. External resistor to ground (Ri) determines internal Reference Bias Current. 15 BRTCurrent Error Amplifier non-inverting input 16 VCOMPVoltage Error Amplifier output. Connects to external frequency compensation capacitor C VCOMP. Controls soft-start timing. 17 VSNSVoltage Error Amplifier inverting input. 18 ICOMPCurrent Error Amplifier output. Connects to external frequency compensation capacitor C ICOMP. 19 ISNSCurrent Error Amplifier inverting Input. 20 OLSNSOpen Lamp Sense Input. 21 TRI_CConnects to external capacitor C TRI for setting strike Frequency ramp slope. 22 VDD 23 VDD_PDedicated VDD for output buffers only. 24 OUT_BOutput driver B.

9. LX1686 Controller Functional Block Diagram 5 Major Blocks –digital dimmer block ( DIMMER BLOCK) –direct drive ramp block ( DDRAMP BLOCK) –direct drive PWM block( PWM BLOCK) –bias control block ( BIAS BLOCK) –output buffer block ( OUT_BUF BLOCK)

10. Theory of Operations- Dimmer Block Performs the frequency locking for a 2Vpp ramp oscillator with oscillation frequency that locks to the LCD display vertical scanning frequency. The VCO is a voltage controlled ramp oscillator with fixed output voltage levels ( 0.5 to 2.5V). In absence of Fvert, the VCO will oscillate at 5/10 its max.frequency. Performs Brite voltage inversion (determined by BRT_POS pad voltage) and past the converted voltage to BRT for analog and digital dimming. Performs the generation of a digital dimming PWM signal derived from the VCOs ramp output with the comparator CMP_D and the external analog DC I/P. When digital dimming is selected, this signal will be synchronised by RAMP_OUT and used to generate 2.5V pulse muxed to port BRT. When analog dimming is selected, then either the BRITE dc voltage or its inverted version will be muxed to the port BRT.

11. Theory of operation- DDRAMP BLOCK Performs the generation of a 2Vpp( 0.25 to 2.25V) ramp oscillator in which its oscillation frequency ( 120k to 240kHz). Ramp oscillator provides 2 timing signal for the controller. Analog ramp output RAMP_C and digital ramp output RAMP_DOUT. Performs frequency sweeping and timing during the CCFL start up mode ( pre- strike) and the run mode ( post strike). Controlled by a 10Hz triangular wave. Detection of lamp condition ( open lamp or lamp ignition) through OLSNS pin.

12. Theory of Operation- PWM BLOCK Performs voltage and current regulation function Performs the transformer voltage regulation by comparator VCMP and error amplifier VAMP. Forms a negative feedback loop to regulate the transformer voltage to a pre- determined value. Performs the lamp current regulation by comparator ICMP and the error amplifier IAMP. Forms a negative feedback loop to regulate the lamp current to a set value determined by the BRT voltage.

13. Theory of Operation- Bias BLOCK Performs the power-down functions controlled by the Enable pin. During power down, no DC power is available to internal circuitry except the ENABLE circuitry. Perform under-voltage-lock-out function. Performs voltage and current bias generation. An internal 2.5V voltage regulator for precision voltage biasing is generated by a band gap circuit. An internal precision current bias is generated through an external resistor Ri at pin I_R. This precision current bias is copied 4 times and distribute to 4 circuit blocks through the ports: I_PD, I_VCO, I_TRI and I_RAMP.

14. LX1688 Targeted directly at high performance monitor market where highly reliable multiple lamp backlight assemblies are used. Important features include lamp failure reporting, open lamp strike time out and the ability to synchronise lamp current frequency and phase for up to 12 controllers. Includes a highly integrated brightness control input that reduces external component count when using either a DC voltage or PWM logic control input.

15. LX1688 Input voltage range 3.0V to 5.5V Standard Analog Dimming W/DC voltage input Digital Dimming –with DC Voltage Input (20:1) –with Digital PWM Input (20:1) Dimming Polarity Selection Enable Polarity Selection Master/ Slave CLK Sync up to 10 controllers Precision Reference voltage OR Switched VDD output –NOT Lamp frequency Sync to Digital Dim Burt Rate –Power up Reset - variable –Auto shut down for open or broken lamp –L amp fault detection w/status reporting output –Patented Direct Drive fixed frequency topology –Digital dimming with digital PWM input –Patented Resonant lamp strike generation technique –Output Open circuit Max voltage regulation –Output Short circuit protection –Sleep mode

16. LX 1688 Block Diagram

17. LX1688 Features Review Operation from 3.3V and/or 5.0V input supply –LX1688 is designed to operate at 3.3V +/- 10% to 5.0V +/- 10%. Under-voltage lock out –set at nominally 2.8V with a 150mV hysteresis Master/ Slave Clock Synchronisation –support upto 12 controllers. –Has two independent oscillators, one for lamp strike and another for lamp run frequency. –Master controller clocks remains at pre-selected frequency for fully ignited lamps even while striking –slave controllers will remains at pre-selected frequency for fully ignited lamp during strike phase –each controller will vary its frequency as needed to strike its lamp, will synchronise with master once lamp is struck. –Master controller clock continue to provide synchronisation to slave even in event of open lamp

18. LX1688 Features Review Fault pin –digital output which indicates the maximum numbers of strike attempts has occurred with lamp ignition –fault pin goes high at fault condition, hold OLSNS low. I_R Pin –set the output frequency through a resistor –output frequency is one half the internal ramp frequency Sleep Mode –consumes less than 10uA ( quisescent current) when ENABLE pin is deactivated

19. LX1689 Originally targeted at PDA market but also an excellent part for notebooks and LCD monitor. On board LDOs permit direct connection to any supply from 3.0 to 28V. Main attributes are savings of from 15 to 30 external components depending on module requirements. Includes internal counter that can synchronise video HSYNC to burst rate. Otherwise functionally nearly identical to LX1686 and could easily replace all LX1686 designs. Includes a automatic 100ms power up delay that holds outputs off during input stabilisation to prevent lamp flashing at system power up.

20. LX1689 Wide Input voltage range 3.0 v to 28v Standard Analog Dimming W/DC voltage input Digital dimming On-chip video Horizontal Sync circuit for digital dimming Dimming Polarity Selection –Lamp frequency Sync to Digital Dim Burst Rate –Power Up Reset –Highly integrated universal PWM&DC Dim Input –Auto shut down for Open or broken lamp –Lamp fault detection w/status reporting output –Patented Direct Drive fixed frequency topology –Digital Dimming with digital PWM input –Patented resonant lamp strike generation technique –Output open circuit maximum voltage regulation –Output short circuit protection –Sleep Mode

21. LX1689 Block Diagram

22. LX1689 Feature Review On-chip LDO regulators.On-chip LDO regulators. –Two LDO regulators extend the input voltage range of the IC with out using external circuitry. Under-voltage lockoutUnder-voltage lockout –when battery input voltage is too low for the controller to function properly, the IC will turn itself off, preventing spurious operation. Power on DelayPower on Delay –delays A and b output turn on for approximately 100mSec after power applied. –Avoid undesirable light flash. Enchanced BRITE Conditioning CircuitryEnchanced BRITE Conditioning Circuitry –able to accept either DC voltage or logic PWM signals. –PWM signals are clipped at 2Volt to avoid lamp current interference from logic amplitude variation.

23. LX1689 Block Diagram

24. LX1689 Pin Description 1 PIN #PIN NAME Description 1 GNDConnects to GND & The Chip Substrate 2 AOUTOutput Buffers A Driver Digital Output: 10Kohm pull down 3 BOUTOutput Buffers B Driver Digital Output: 10Kohm pull down 4 DIM_CLKDigital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for Digital Dimming. This input can be any clock signal up to 200KHz. This pin is also used to control the dimming polarity when operating in the analog or internal digital mode. If DIM_MODE is in the open condition (Analog Dimming Mode) the DIM_CLK input should be left open or VDD_A/2 for conventional dimming polarity or set to Ground for reverse polarity. Conventional polarity means that lamp brightness increases with increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness decreases with increasing voltage. 5 DIM_MODEDimming Mode Input. This three state input pin places the IC in Analog Dimming Mode, internal Digital Dimming Mode, or external Digital Dimming Mode. If the input is left open or forced to VDD_A / 2 Analog mode is selected. If connected to VDD_A, Digital Dimming with the external clock source applied to the DIM_CLK input is selected to the burst timing generator. If connected to Ground, Digital Dimming with an internal clock is selected. The internal clock is equivalent to the frequency at AOUT divided by two

25. LX1689 Pin Description 2 PIN #PIN NAME Description 6 DIV_248Divide Digital Dimming clock by 2, 4, or 8. This three state input pin cause the internal or external digital dimming clock source to be divided by one of the three values, 2, 4, or 8. Its purpose is to allow a selection of three possible burst rates for any given external or internal clock source. A high (VDD_P) selects divide by 2, open selects divide by 4, and ground selects divided by 8. See Table 1 for possible burst rates for common display resolutions. We advise keeping burst above 95Hz and below about 400HZ. This will minimize visible flicker and possible audible noise from the power supply components. 7 BRITE_CBRITE Filter Capacitor and FAULT Output. Used to filter DC Input voltages or to convert higher frequency digital PWM inputs to proportional DC currents at the BRITE_OUT pin. The capacitor forms a low pass filter with an internal 200K resistor. This pin will be driven to VDD_P if a lamp strike fault is detected by the LX1689. If no fault is present the voltage at this pin will vary from 0.1 to 1.1V as BRITE_IN varies from 0 to 2V. A CMOS gate may be connected to this pin to sense the fault condition. TTL gates or other low impedance (less than 20 Mohm) must not be connected to this node as their DC resistance will load the internal 200K resistor and create error in the BRITE_OUT current level. 8 BRITE_RDedicated Bias resistor for BRITE_OUT current source.

26. LX1689 Pin Description 3 PIN #PIN NAME Description 9 BRITE_INBrightness Control Input. The input signal can be a DC voltage, a low frequency pulse width modulated digital signal, or a high frequency pulse width modulated digital signal. Active DC voltage range is 0.5 to 2.0V Signals above 2V are clipped and signals below 0.5V make output current from the BRITE_OUT pin equal zero. Low frequency digital PWM signals up to 3KHz can be applied to affect Digital Dimming. Higher frequency PWM signals, up to 100KHz are filtered to an equivalent DC current at the BRITE_OUT pin by adding a capacitor at the BRITE_C pin. On chip signal conditioning amplifiers clip inputs above 2V so that lamp current amplitude is not sensitive to the voltage level variations of a digital PWM input signal. Maximum input voltage at the BRITE_IN pin is 5.5VDC 10 ENABLEChip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the V _BATT pin, disabling all functions. Logic threshold is 1.3 ± 0.2V maximum over supply and temperature range. Maximum current into V_BATT when ENABLE < 0.3V, V_BATT <28V, is 28 µA; and 15µA at V_BATT = 15V ENABLE may be connected to V_BATT through a series resistor if the disable function is not used. Resistor tolerance is ± 10%; and R value is: R=(VBAT MIN -1.5)/30000 [KOHM] The Enable pin can be connected directly to 3.3V logic.

27. LX1689 Pin Description 4 PIN #PIN NAME Description 11 I_RCurrent Reference Resistor Input. Connects to an external resistor that determines the magnitude of internal bias currents. The nominal lamp frequency can be adjusted by varying this resistor value in the range of 40K to 100K Ohms. I_R= 1.0/R I_R 12 EA_INError Amp Inverting Input. Frequency Compensation input for the Error Amplifier. See EA_OUT below. A 100K, negative TC on chip resistor connected between the inverting input of the error amplifier and the output of the I_SNS full wave rectifier is the resistor in an R/C compensation network. Resistance may range from 30%. 13 EA_OUTError Amp Output. Frequency Compensation output for the Error Amplifier. An external capacitor is connected from this pin to EA_IN to adjust loop response of the inverter module. This capacitor value can vary from 10pF to 5000pF in various applications. 14 BRITE_OUTBrightness Reference Current Output. This variable current source is the mirror of BRITE_R current multiplied by the voltage at BRITE_C (0 to 1.0V) when analog dimming is selected or by 1.0V when digital dimming is selected, becomes the reference voltage to the lamp current error amplifier when applied to an external precision resistor connected from the BRITE_OUT pin to ground. BRITE_OUT current:

28. LX1689 Pin Description 5 PIN #PIN NAME Description 15 I_SNSCurrent Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp current. The I_SNS input is full wave rectified and amplified, then presented to the inverting input of the current error amplifier through a 100K, 5% resistor. Frequency range of the input signal is 10 to 500KHz. Normal operating voltage levels will be in the range of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault conditions. Transient under fault conditions can reach ± 25VPK. Input voltage of up to ± 2.5V peak are linearly rectified. Input voltage above ± 2.5V peak but less than ±25V peak may cause saturation but do not cause malfunction, phase reversal, or reliability issues with the IC. 16 OV_SNSOver Voltage Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp voltage. The OV_SNS input will be full wave rectified, then applied to a digital comparator with a 2V reference to cause peak voltage greaten than 2V to digitally reset the PWM logic on a pulse by pulse basis. Frequency range of the input signal is 10Khz to 500KHz. Normal operating voltage levels will be in the range of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ±10V peak under load fault conditions. Transients under fault conditions can reach ± 25VPK. Input voltage of up to ± 2.5V peak but less than ± 25V peak may cause saturation but should not cause malfunction, phase reversal, or reliability issues with the IC. The input will have a 10K ± 3K (max over temperature) pull down resistor that serves as a DC restorer to the external capacitor that divides down lamp voltage.

29. LX1689 Pin Description 6 PIN #PIN NAME Description 17 OC_SNSOver Current Sense Input. A full wave AC voltage input centered on ground that is proportional to total high voltage transformer secondary winding current. The OC_SNS input is full wave rectified, then applied to a digital comparator with a 2V reference to cause peak voltages greater than 2V to digitally reset the PWM logic on a pulse by pulse basis. Frequency range of the input signal is 10kHz to 500KHz. Normal operating voltage levels will be in the range of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault conditions. Transients under fault conditions can reach ± 25VPK. Input voltage greater than ± 2.5V peak but less than ± 25V peak may cause saturation but will not cause malfunction, phase reversal, or reliability issues with the IC. 18 VBATVoltage Input, 2.80 to 28V input range. V _BATT is switched (see ENABLE) to remove power from chip. Two LDO regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to the VDD_A output. 19 VDD_AAnalog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on chip VDD_A LDO regulator. The input of the LDO is the switched V _BATT supply. LDO output is normally 3.15V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Drop out voltage is less than 0.3V at 10mA. Average internal load is 5mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the combination of output current and input voltage exceeds power dissipation capability of the die. The external capacitor will be a 100 to 1000nF ceramic dielectric type.

30. LX1689 Pin Description 7 PIN #PIN NAME Description 20 VDD_PPower VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on chip VDD_P LDO regulator. The input of the LDO is the switched V _BATT supply. LDO output is normally 5.5V and is used only to drive the output buffers at A OUT and B OUT. Drop out voltage is less than 0.3V at 10mA. Maximum average current to the buffers is 10mA. The external capacitor will be a 100 to 1000nF ceramic dielectric.

31. LX1689 Feature Review Digital or Analog Dimming modeDigital or Analog Dimming mode –analog mode, the lamp current amplitude is controlled via the Brite In –digital mode, control the duty cycle with amplitude fixed at a nominal value. –In digital mode, the dimming burst frequency can be synchronise by either the internal clock or external clock. –Three burst rate selection, by programming the DIV_248 pin. Lamp current compensationLamp current compensation –allows designer to compensate lamp current with respect to temperature, input voltage, ambient or lamp light output. –Useful in automotive and outdoor applications where operating temperatures and ambient light vary over wide ranges. Strike Voltage GenerationStrike Voltage Generation –improved strike voltage generation, ramp strike to maximum potential and hold for 2 seconds to insure a worst case lamp strike at any temperature. –Strike potential removed when 2 seconds limit is up.

32. LX1689 Feature Review Strike DetectionStrike Detection –monitor lamp current pulses to determine if the lamp strike On Chip RectifiersOn Chip Rectifiers –On chip rectification improved the current and voltage regulation and significantly reduced the lamp feedback component count. Fault Time OutFault Time Out –output drive will be shut down and Brite_C pin is driven high if the lamp fails to ignite with in the 2 seconds strike potential or lamp extinguishes erroneously. Complete Fault ProtectionComplete Fault Protection –lamp fault condition ( open, short, either lamp terminal shorted to ground) are detected.

33. LX1686 vs LX1689