1. Analysis of Floorplanning Algorithm in EDA Tools
By:
RENISHKUMAR V. LADANI
M.TECH-2003, DA-IICT
GANDHINAGAR
GUIDE: PROF. ASHOK AMIN
CO-GUIDE: PROF. AMIT BHATT

2. Floorplanning in context of VLSI physical Design
Bottom-up methodology
Top-down methedology:FLOORPLAN-BASED DESIGN METHODOLOGY

3. Floorplanning in context of VLSI physical Design
Bottom-up methodology
May leads to poor utilization of the chip area and excessive wiring
Top-down methedology:FLOORPLAN-BASED DESIGN METHODOLOGY
It advocates that layout aspects should be taken into account in all design stages.
Advantege:
Gives early feed back
Suggests valuable architectural modifications
Estimates the whole chip area
Estimates wire length
Estimates delay and congestion due to wiring

4. Floorplan Example

5. Floorplanning Problem
Input to the floorplanning problem:
A set of blocks, hard of soft
Pin locations of hard blocks
A netlist (interconnect pattern)
Output expected from the floorplanning problem:
Shapes of soft blocks
Position of each blocks in final layout
Objectives:
Minimize area
Reduce wirelengths
Maximize routability (minimize congestion)
Delay of critical path
Noise, heat dissipation, etc.

6. Wire length Estimation
The Cost Function
Cost = *Atot + *Wtot
Where,
Atot = Total area of the packing.
Wtot = Total wire length of packing.
 and  = User specified constant.
Wire length Estimation
Exact wire length of each net is not known until routing is done and also pin positions are not known yet for soft blocks
Two ways of wire length estimation
center-to-center estimation
half-perimeter estimation

7. Some Constraints in Floorplanning
Preplaced constraint
Boundary constraint
Range constraint
Note that in floorplanning some times L-shaped, U-shaped blocks are being considered in addition to rectangular blocks.
Floorplan Sizing: A optimization problem in Floorplanning
The availability of flexible blocks implies the possibility of having different shapes for the same hardware units. Its therefore possible to choose a suitable shape for each flexible blocks such that the resulting floorplan is optimal in some sense (e.g. minimal area).

8. Floorplanning Concepts and Approaches to Problem
The floorplan problem is known to be NP-complete
Various heuristic approaches
Simulated Annealing (SA)
Genetic Algorithm (GA)
Hybrid approach(SAGA: simulated annealing and genetic algorithm)
These algorithms depend on representation of feasible solution space
Classification of representation:
Slicing floorplan representation
Non-slicing floorplan representation

9. Slicing Structure
Rectangular Dissection: Subdivision of a given rectangle by a finite # of horizontal and vertical line segments into a finite # of non-overlapping rectangles.
Slicing structure: A rectangular dissection that can be obtained by repetitively subdividing rectangles horizontally or vertically.
Slicing tree: A binary tree, where each internal node represents a vertical cut line or horizontal cut line, and each leaf a basic rectangle.
Polish expression: Expression obtained Post order traversal of slicing tree. (16+35*2+74+**)
Wong and Liu proposed an algorithm based on simulated annealing for slicing floorplan designs using a normalized polish expression(extension of polish expression) to represent a slicing structure.

10. Non-Slicing Structure
Not all floorplans are slicing
If the basic rectangles corresponding to leaf nodes in slicing structures can not be obtained by recursive cutting rectangles into smaller rectangles then the floorplan has non-slicing structure
Non-Slicing Floorplan Representation
Sequence Pair(SP)
Bounded Slicing Grid (BSG)
O-tree
Transitive Closure Graph (TCG)
Corner Block List (CBL)
B* Trees
Generalized Polish Expression(GPE)

11. Simulated annealing
Well-known high performance optimization technique for combinatorial problems
01 Temperature = Intial Temperature;
02 Current placement = Random initial placement;
03 Current score = Score( Current placement);
04 While equilibrium at temperature not reached Do
05 Selected component = Select (at random);
06 Trail placement = Move (selected component);
07 Trail score = Score (trail placement);
08 If trail score < current score then
09 Current score = trial score;
10 Current placement = trail placement;
11 else
12 if uniform random(0,1) < e-(trail score – current score)/temperature then
13 Current score = trial score;
14 Current placement = trail placement;
15 temperature = temperature * Alpha; // alpha ~ 0.95

12. Comparisons between slicing and non-slicing approach
Slicing representation
Advantages:
Smaller encoding cost and solution space bringing faster runtime for packing
Flexible to deal with hard, preplaced, soft and rectilinear blocks
Disadvantages:
Optimal solution might not be in the solution space of slicing structure
Non-slicing representation
Optimal solution might be achieved.
Needs more evaluating runtime for packing

13. State-of-art in floorplan representationsSP
Fast-SP
BSG
O-tree
B*-tree
CBL
TCG
GPE
Is P-admissible?
Yes No
Need sequence
encoding?
Constraint graphs
for packing?
Solution space
size
n!2
2n(n+2)
O(n!22n-2 /n1.5)
O(n!23n-3 /n1.5)
O(n!23n-3 /n1.5)
N!2 -
Runtime for
packing
O(n2)
O(n lg n lg n)
O(n)
Number of bits to
describe floorplan
2n[lg n]
2n[lg n]
2n+n[lg n]
6n+n[lg n]
3n+n[lg n]
Table 1: Properties of representations. Here, n is the number of modules in the placement.

14. State-of-art in floorplan representations
Table 2: Comparisons for runtime and area requirements among O-TREE, B*-TREE, CBL, SP and TCG based on genetic and simulated annealing algorithms. (NA: NOT AVAILABLE)
It is important to note that GPE achieves area utilization compared to previous Fast-SP and Enhance O-tree.

15. GPE: Generalized Polish Expression
New and easy representation for VLSI floorplan
Effectively inherits the useful property of Normalized Polish Expression for slicing structure
Present non-slicing floorplan
The time complexity to transform a GPE to a corresponding placement is O(n).

16. Future planning
Note sizing means handling soft(flexible) blocks while floorplanning.
Floorplan sizing can be done optimally and efficiently for slicing floorplans
“Shape Curve Computation” used for sizing flexible blocks
Sizing algorithm runs in polynomial time
Floorplan sizing can be done optimally but not efficiently for some slicing non-slicing floorplans, which are using Constraints Graph for packing such as SP, Fast-SP, O-tree and B-tree.
GPE a new representation for non-slicing floorplans, which has achieved promising result in area utilization as compared to Fast-SP and O-tree.
Since its inherits properties from polish expression for which sizing (shaping for soft blocks) can be done in polynomial time, it raises hopes that with GPE sizing can be done in less time then timing required by sizing for Non slicing floorplans.
Study for handling soft(flexible) blocks has been not carried out.

17. Thanks
Question and Answer