Thomas L. Floyd Digital Fundamentals, 9e

Name: Thomas L. Floyd Digital Fundamentals, 9e
Uploaded: 2017-08-09T10:03:17+00:00
Duration: PTM17S54
Channel: Walker Redfearn
Description: Thomas L. Floyd Digital Fundamentals, 9e

Figure 13–1 An original analog signal (sine wave) and its “stairstep” approximation.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13–2 Basic block diagram of a typical digital signal processing system.

Figure 13–3 Illustration of the sampling process.

Figure 13–4 Bouncing ball analogy of sampling theory.

Figure 13–5 A basic illustration of the condition fsample < 2fa(max).

Figure 13– After low-pass filtering, the frequency spectra of the analog and the sampling signals do not overlap, thus eliminating aliasing error. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13–7 Illustration of a sample-and-hold operation.

Figure 13– Basic function of an analog-to-digital (ADC) converter (The binary codes and number of bits are arbitrarily chosen for illustration only). The ADC output waveform that represents the binary codes is also shown. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13– Sample-and-hold output waveform with four quantization levels. The original analog waveform is shown in light gray for reference. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13– The reconstructed waveform in Figure 13–9 using four quantization levels (2 bits). The original analog waveform is shown in light gray for reference. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13– Sample-and-hold output waveform with sixteen quantization levels. The original analog waveform is shown in light gray for reference. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13– The reconstructed waveform in Figure 13–11 using sixteen quantization levels (4 bits). The original analog waveform is shown in light gray for reference. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13–13 The operational amplifier (op-amp).

Figure 13–14 A 3-bit flash ADC.

Figure 13–15 Sampling of values on a waveform for conversion to binary code.

Figure 13–16 Resulting digital outputs for sample-and-hold values
Figure 13– Resulting digital outputs for sample-and-hold values. Output D0 is the LSB of the 3-bit binary code. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13–17 Basic dual-slope ADC.

Figure 13–18 Illustration of dual-slope conversion.

Figure 13–19 Successive-approximation ADC.

Figure 13–20 Illustration of the successive-approximation conversion process.

Figure 13–21 The ADC0804 analog-to-digital converter.

Figure 13–22 A simplified illustration of sigma-delta analog-to-digital conversion.

Figure 13–23 Partial functional block diagram of a sigma-delta ADC.

Figure 13–24 One type of sigma-delta ADC.

Figure 13–25 A method for testing ADCs.

Figure 13–26 Illustrations of analog-to-digital conversion errors.

Figure 13–27 Thomas L. Floyd Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 13–28 The DSP has a digital input and produces a digital output.

Figure 13–29 Simplified block diagram of a digital cellular phone.

Figure 13–30 Many DSPs use the Harvard architecture (two memories).

Figure 13–31 General block diagram of the TMS320C6000 series DSP.

Figure 13–32 The four fetch phases of the pipeline operation.

Figure 13–33 The two decode phases of the pipeline operation.

Figure 13–34 The five execute phases of pipeline operation.

Figure 13–35 A 352-pin BGA package.

Figure 13–36 A 4-bit DAC with binary-weighted inputs.

Figure 13–38 Output of the DAC in Figure 13–37.

Figure 13–39 An R/2R ladder DAC.

Figure 13–40 Analysis of the R/2R ladder DAC.

Figure 13–41 Basic test setup for a DAC.

Figure 13–42 Illustrations of several digital-to-analog conversion errors.

Figure 13–44 The reconstruction filter smooths the output of the DAC.

Thomas L. Floyd Digital Fundamentals, 9e

Similar presentations

Presentation on theme: "Thomas L. Floyd Digital Fundamentals, 9e"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Thomas L. Floyd Digital Fundamentals, 9e

Similar presentations

Presentation on theme: "Thomas L. Floyd Digital Fundamentals, 9e"— Presentation transcript:

Similar presentations

About project

Feedback