1. CENG 241 Digital Design 1 Lecture 3 Amirali Baniasadi amirali@ece.uvic.ca

2. 2 This Lecture zReview of last lecture zBoolean Algebra

3. 3 Canonical & Standard Forms zConsider two binary variables x, y and the AND operation zfour combinations are possible: x.y, x’.y, x.y’, x’.y’ zeach AND term is called a minterm or standard products zfor n variables we have 2 n minterms zConsider two binary variables x, y and the OR operation zfour combinations are possible: x+y, x’+y, x+y’, x’+y’ zeach OR term is called a maxterm or standard sums zfor n variables we have 2 n maxterms

4. 4 Minterms zx y z Terms Designation z 0 0 0 x’.y’.z’ m0 z 0 0 1 x’.y’.z m1 z 0 1 0 x’.y.z’ m2 z 0 1 1 x’.y.z m3 z 1 0 0 x.y’.z’ m4 z 1 0 1 x.y’.z m5 z 1 1 0 x.y.z’ m6 z 1 1 1 x.y.z m7

5. 5 Maxterms zx y z Designation Terms z 0 0 0 M0 x+y+z z 0 0 1 M1 x+y+z’ z 0 1 0 M2 x+y’+z z 0 1 1 M3 x+y’+z’ z 1 0 0 M4 x’+y+z z 1 0 1 M5 x’+y+z’ z 1 1 0 M6 x’+y’+z z 1 1 1 M7 x’+y’+z’

6. 6 Boolean Function: Exampl How to express algebraically z1.Form a minterm for each combination forming a 1 z2.OR all of those terms zTruth table example: zx y z F1 minterm z 0 0 0 0 z 0 0 1 1 x’.y’.z m1 z 0 1 0 0 z 0 1 1 0 z 1 0 0 1 x.y’.z’ m4 z 1 0 1 0 z 1 1 0 0 z 1 1 1 1 x.y.z m7 zF1=m1+m4+m7=x’.y’.z+x.y’.z’+x.y.z=Σ(1,4,7)

7. 7 Boolean Function: Exampl How to express algebraically z1.Form a maxterm for each combination forming a 0 z2.AND all of those terms zTruth table example: zx y z F1 maxterm z 0 0 0 0 x+y+z M0 z 0 0 1 1 z 0 1 0 0 x+y’+z M2 z 0 1 1 0 x+y’+z’ M3 z 1 0 0 1 z 1 0 1 0 x’+y+z’ M5 z 1 1 0 0 x’+y’+z M6 z 1 1 1 1 zF1=M0.M2.M3.M5.M6 = л(0,2,3,5,6)

8. 8 Implementations Three-level implementation vs. two-level implementation Two-level implementation normally preferred due to delay importance.

9. 9 Digital Logic Gates

10. 10 Integrated Circuits (ICs) zLevels of Integration zSSI: fewer than 10 gates on chip zMSI:10 to 1000 gates on chip zLSI: thousands of gates on chip zVLSI:Millions of gates on chip z Digital Logic Families zTTL transistor-transistor logic zECL emitter-coupled logic zMOS metal-oxide semiconductor zCMOS complementary metal-oxide semiconductor

11. 11 Digital Logic Parameters zFan-out: maximum number of output signals zFan-in : number of inputs zPower dissipation zPropagation delay zNoise margin: maximum noise

12. 12 Gate-Level Minimization zThe Map Method: zA simple method for minimizing Boolean functions zMap: diagram made up of squares zEach square represents a minterm

13. 13 Two-Variable Map

14. 14 Two-Variable Map Maps representing x.y and x+y

15. 15 Three-Variable Map

16. 16 Three-Variable Map Minterms are not arranged in a binary sequence Minterms arranged in gray code: Only one bit changes from one column to the next

17. 17 Three-Variable Map Each variable is 1 in 4 squares, 0 in 4 squares Variable appears unprimed in squares equal to 1 Variable appears primed in squares equal to 0 Each variable is 1 in 4 squares, 0 in 4 squares

18. 18 Three-Variable Map-example 1 Sum of two adjacent minterms can be simplified to a single AND term consisting of two literals

19. 19 Three-Variable Map-example 2

20. 20 Three-Variable Map-example 3

21. 21 Three-Variable Map-example 4

22. 22 Four-Variable Map

23. 23 Four-Variable Map-example 1 1

24. 24 Four-Variable Map-example 2

25. 25 HW #1 zHW #1- Due Friday, May 23rd (4:00 PM) zSolve the following problems from the textbook (5th edition): 2-20, 2-21. 3-2, 3-4, 3-5 and 3-12.

26. 26 Summary zExtension to multiple inputs zPositive & Negative Logic zIntegrated Circuits zGate Level Minimization