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Ain Shams University Faculty of Engineering Integrated Circuits Lab VLSI Design and Implementation of ASICs for the Security Core of BLUETOOTH Wireless Communication System Standard Presented By: Sameh Assem Ibrahim Ahmad Abdelhameed
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16 – July - 2001 2/16 IntroductionAuth. & Key gen.EncryptionSecurity coreASIC/FPGA Introduction Bluetooth Security Key generation EncryptionAuthentication Bluetooth Baseband Correction Error Correction Hop Selection SecurityOthers BluetoothArchitecture Bluetooth ArchitectureRF Baseband Manager Link Manager SoftwareLayers Software Layers
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16 – July - 2001 3/16 Authentication & Key Generation Design Goals E 1, E 21, E 22 and E 3 algorithms implementation IntroductionEncryptionSecurity coreASIC/FPGA
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16 – July - 2001 4/16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA Ar/Ar’ Controller Input preparation Feedback operations output Block Diagram
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16 – July - 2001 5/16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA Key Schedule SAFER+ Encryption Round Controller output Final round operations Feedback operations In case of Ar’ Ar/Ar'
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16 – July - 2001 6/16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA SequentialCombinational Key Schedule
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16 – July - 2001 7/16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA Sequential SAFER+ Encryption Round Combinational
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16 – July - 2001 8/16 Authentication & Key Generation IntroductionEncryptionSecurity coreASIC/FPGA GUI MATLAB program for simulation
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16 – July - 2001 9/16 Encryption Input Shuffling (confusion and diffusion)Input Shuffling (confusion and diffusion) Summation Stream Cipher (Massey - Rueppel)Summation Stream Cipher (Massey - Rueppel) Encryption Engine IntroductionAuth. & Key gen.Security coreASIC/FPGA
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16 – July - 2001 10/16 Encryption Block Diagram IntroductionAuth. & Key gen.Security coreASIC/FPGA
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16 – July - 2001 11/16 Security CoreFeatures: Key generation : E 21, E 22, E 3Key generation : E 21, E 22, E 3 Authentication : E 1Authentication : E 1 Encryption : E 0Encryption : E 0 Built in PRNG : 128 bitsBuilt in PRNG : 128 bits Built in S/P & P/SBuilt in S/P & P/S Built in ControllerBuilt in Controller Pseudo-Random Number Generator Proposed Design IntroductionAuth. & Key gen.EncryptionASIC/FPGA
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16 – July - 2001 12/16 ASIC/FPGA Back Annotation All Controls (Modified) S10PC84 IntroductionAuth. & Key gen.EncryptionSecurity core
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16 – July - 2001 13/16 ASIC/FPGA FPGA tests IntroductionAuth. & Key gen.EncryptionSecurity core
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16 – July - 2001 14/16 ASIC/FPGA FPGA Reports *************************************************** Device Utilization for S10PC84 *************************************************** Resource Used Avail Utilization --------------------------------------------------- IOs 32 61 52.46% FG Function Generators 233 392 59.44% H Function Generators 7 196 3.57% CLB Flip Flops 294 392 75.00% --------------------------------------------------- Clock Frequency Report Clock : Frequency --------------------------------------------- CLK : 55.3 MHz S10PC84 EncryptionEngine Number of ports : 45 Total accumulated area : Number of Dffs or Latches : 2553 Number of Function Generators : 4948 Number of MUX CARRYs : 1006 Number of MUXF5 : 367 Number of MUXF6 : 110 Number of gates : 4752 *************************************************** Device Utilization for v1000fg680 *************************************************** Resource Used Avail Utilization --------------------------------------------------- IOs 45 512 8.79% Function Generators 4948 24576 20.13% CLB Slices 2474 12288 20.13% Dffs or Latches 2553 24576 10.39% --------------------------------------------------- Clock : Frequency --------------------------------------------------- clk : 66.2 MHz V1000FG680 SecurityCore IntroductionAuth. & Key gen.EncryptionSecurity core
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16 – July - 2001 15/16 ASIC/FPGA ASIC flow AMS 0.6 µm technology Double metal layers Single poly Core Area: 12.04 mm 2 IntroductionAuth. & Key gen.EncryptionSecurity core
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16 – July - 2001 16/16
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