1. Yakir Vizel 1,2 and Orna Grumberg 1 1.Computer Science Department, The Technion, Haifa, Israel. 2.Architecture, System Level and Validation Solutions, Intel Development Center, Haifa, Israel Formal Methods in Computer Aided Design, Austin, Texas 2009 1

2.  Introduction  Model checking  Forward Reachability Analysis  Bounded Model Checking  Interpolation  Interpolation  Interpolation-Sequence  Interpolation-Sequence Based Model Checking  Experimental Results Formal Methods in Computer Aided Design, Austin, Texas 2009 2

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4.  Given a system and a specification, does the system satisfy the specification. Formal Methods in Computer Aided Design, Austin, Texas 2009 4 SystemAGq MC ?  The specification is given in temporal logic – e.g. LTL.  We deal with specifications of the form AGq.

5. …… S n S 2 S1S1 S1S1 INIT BAD ¬q Formal Methods in Computer Aided Design, Austin, Texas 2009 5

6.  Does the system have a counterexample of length k? Formal Methods in Computer Aided Design, Austin, Texas 2009 6......

7. INIT I3I3 I3I3 BAD ¬q I1I1 I1I1 I2I2 I2I2 S1S1 S 1 S2S2 S 2 S3S3 S 3 7

8. Formal Methods in Computer Aided Design, Austin, Texas 2009 8

9. 9  Given the following BMC formula. A B I

10. Formal Methods in Computer Aided Design, Austin, Texas 2009 10 A1A1 A2A2 A3A3 AkAk A k+1 I1I1 I2I2 I3I3 I k-1 IkIk  The same BMC formula partitioned in a different manner:

11.  Can easily be computed. For 1 ≤ j < n  A = A 1  …  A j  B = A j+1  …  A n  I j is the interpolant for the pair (A,B) Formal Methods in Computer Aided Design, Austin, Texas 2009 11

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13. I 1,1 Formal Methods in Computer Aided Design, Austin, Texas 2009 I 1,2 I 2,2 I1I1 I1I1 13

14.  A way to do reachability analysis using a SAT solver.  Uses the original BMC loop and adds an inclusion check for full verification.  Similar sets to those computed by Forward Reachability Analysis but over- approximated. Formal Methods in Computer Aided Design, Austin, Texas 2009 14

15.  Use BMC to search for bugs.  Partition the checked BMC formula and extract the interpolation sequence Formal Methods in Computer Aided Design, Austin, Texas 2009 I 1,N I N-1,N I 2,N I N,N 15

16. Formal Methods in Computer Aided Design, Austin, Texas 2009 INIT S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 I1I1 I1I1 I2I2 I2I2 I3I3 I3I3 BAD ¬q I 1,1 I 2,2 I 1,2 I1I1 I1I1 I2I2 I2I2 I 3,3 I 2,3 I 1,3 16

17.  The computation itself is different.  Uses basic interpolation.  Successive calls to BMC for the same bound.  Not incremental.  The sets computed are different. Formal Methods in Computer Aided Design, Austin, Texas 2009 17 S1S1 S1S1 I1I1 I1I1 J1J1 J1J1

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19.  Experiments were conducted on two future CPU designs from Intel (two different architectures/tocks) Formal Methods in Computer Aided Design, Austin, Texas 2009 19

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22. Formal Methods in Computer Aided Design, Austin, Texas 2009 Spec#VarsBound (Ours) Bound (M) #Int (Ours) #Int (M) #BMC (Ours) #BMC (M) Time [s] (Ours) Time [s] (M) F1F1 340616151368016809705518 F2F2 17539845409 91388 F3F3 175316151369416944731901 F4F4 34066521136 68208 F5F5 176121322254 F6F6 39723163331914 F7F7 219731633325441340 F8F8 48945115353635101 22

23.  False properties is always faster.  True properties – results vary. Heavier properties favor ISB where the easier favor IB.  Some properties cannot be verified by one method but can be verified by the other and vise-versa. Formal Methods in Computer Aided Design, Austin, Texas 2009 23

24.  A new SAT-based method for unbounded model checking.  BMC is used for falsification.  Simulating forward reachability analysis for verification.  Method was successfully applied to industrial sized systems. Formal Methods in Computer Aided Design, Austin, Texas 200924

25. Thank You! Formal Methods in Computer Aided Design, Austin, Texas 2009 25