1. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk1 Forward Multiplicity Detector (status and progress) Si-FMD (Forward Multiplicity Detector) oSi-strip Ring counters (5) with 50.000 channels o-5.1<  < -1.7; 1.7<  < 3.4 oOff-line charged particle multiplicity for A+A, p+p oFluctuations event-by-event, flow analysis oGeometry and integration defined.Prototyping of mech. Supports. oFinal Si-sensor design ongoing. oRead out chain (FEE-BEE-DAQ) defined.Prototyping ongoing. oPerformance/simulations oTDR in preparation. oConcerns: ’ambient’ temperature, material

2. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk2 Si-FMD  5 Si-strip rings segmented into 50.000 channels  Rapidity coverage from ITS (1.7) to 5.1.  Segmentation sufficient for ‘Poisson’ analysis Main Off-line charged particle multiplicity studies Average multiplicity (entropy, stopping) Fluctuations (phase transitions) Flow (thermalisation, hydrodynamics) Si3 Si2 Si1

3. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk3 Forward rapidity physics at LHC pppp BRAHMS@ RHIC  s nn = 200AGeV Plateau at LHC –6<  <+6 ?

4. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk4 CERN Maquette 1:1 Si1 (inner)Si1(outer) V0-R T0-R Absorber ITS-pixels

5. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk5 Mechanical Installation

6. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk6 FMD Cabling on muon side Digitized signals, HV and control

7. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk7 Si1 mechanics model 1:1 Si detectors Support plate Digitizer card Beam pipe support ring Outer ring not shown Engineering study in progress to minimize material, maximize rigidity

8. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk8 Heat dissipation oHeat dissipated by FE electronics of one Si detector ring: VA1’’ preamp chip (128 channels): 235 mW  80 chips = 19 W / ring Read-out electronics and power distribution:  5 W/ring Cooling: air flow between Si detector and support plate radiation from VA chips to support. active (water) cooling of support plate is considered Detailed cooling studies (simulations of heat profile) need to be done. Presently, the temperature at the FMD, T0, V0 location is >70 deg. due to ITS heat dissipation. Effective general cooling of this region required !

9. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk9 Left Side: Si2 & Si3 Details of mounting to be finalized

10. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk10 Si rings manufactured of 6” wafers 512 Inner: Rin=4.2 cm Rout=17.2 cm Outer: Rin=15.4 cm Rout=28.4 cm 10x2x512=10240 20x2x256=10240 256 Possible suppliers: Micron, UK Hamamatsu, JP

11. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk11 Coverage in pseudorapidity Constraints: Vacuum tube outer envelope: 42 mm, Outer radius, ITS, Absorber, cables Background from secondaries(small angles) Design criteria: Largest possible  coverage Largest symmetry left and right Overlap between systems Si1: Out: 1.70<  <2.29 In: 2.01<  <3.40 Si2: Out: -2.29<  <-1.7 In: -3.68<  <-2.28 Si3: In: -5.09<  <-3.68 Vertex shift (10cm): |d  |  0.1 

12. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk12 Details of Si sensors Hamamatsu, Micron

13. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk13 Adjusted acceptance

14. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk14 Hybrid with Viking PA chips VA preamp+shaper: 128 ch Connector(s) for power, control, read-out Other components Hybrid cards contain:  FE–Preampl. chips  Bias voltages distribution  Gate/strobe distribution  Read-out clock distribution  Detector bias connection Si detector

15. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk15 FMD RO strategy FMD Segment ON DETECTOR Digital serial links (15-20 m) Digital serial links (15-20 m) Trigger & Slow Ctrl IN CAVERN IN COUNTING ROOM Slow control & Trigger Slow control & Trigger Detector Data Link (50-60 m) Detector Data Link (50-60 m) FMD RCU VA 1 ring: 10/20 segments 2 Digitizers 1 RCU per side 1 DDL per side Full FMD: 70 segments 10 Digitizers 2 RCU’s 2 DDL’s FMD Read-Out and Control Electronics Analog serial link (10 MHz)  0.5 m Analog serial link (10 MHz)  0.5 m VA read-out control VA read-out control Local Controller DDL - INT Slow-Control Interface TTC-RX BOARD CTRL Data receiver FMD Digitizer ALTRO CTRL Read-out CTRL CTRL BSN, 21 Nov 2002

16. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk16 Si-FMD electronics overview SI-FMD channel count Note: We have increased the number of strips, but use more integrated FE chips – red values are changed. Segments (wafers) Phi sectors Radial strips FE channels VA chips (128 ch/chip) ALTRO chips FMD Digitizers FMD RCU Si1 inner102051210,24080621 Si1 outer204025610,2408062 Si2 inner102051210,2408062 Si2 outer204025610,24080621 Si3102051210,2408062 Total system 7014051,20040030102

17. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk17 FMD FEE test setup BSN, 21 Nov 2002 FMD FEE test CTRL Power Biases Power Biases Clock 10 MHz Clock 10 MHz Trig in ALTRO tester ALTRO CTRL Ext clock Ext trigger Si detector VA Labview DAQ NBI test board: - generates trigger + pulse on Si det - level adaption of VA-to-ALTRO - VA read-out clock + controls - ALTRO digitization clock (sync.)

18. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk18 Si-FEE-Digitizer prototyping at NBI ALTRO tester Si-strip detector + VA’’ preamp VA’’ read-out controller DAQ/ Labview

19. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk19 First prototype test results Trigger Si+ Preamp Out Altro Out Output from VA chip: (128 channels multiplexed into serial read-out) Note: 3 bad Si/VA channels Output from ALTRO: (128 time bins are digitized) Note: general shape + 3 bad channels repeated Noise still too high Timing still not stable

20. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk20 Slow Controls Follow main strategy DCS Detector CAEN ? PVSS II Preamps CAEN ? Ethernet Database(s) OPC client DIM client 14070 11 High Voltage Preamps User interface PVSS II HVLV FMD Control room (ACR) [FSM?] Crate Control PCI-CAN? CAEN OPCserver PVSS II OPS client PCI-CAN? CAEN OPCserver PVSS II OPC client DIMserver Digitizers FMD Digitizers PCI-CAN? ? PVSS II OPC client C 2 28/02/03 EE FMD-RCU (PCI? VME?) 20 LV P 2 DDL PCI-Profibus Ethernet is considered as alternative P? 10 300? 10 LVL 0 trig TTC Counting room Cavern In magnet

21. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk21 Charged particle occupancy including secondaries 20  sectors 512 strips each 10240 channels 20  sectors 512 strips each 10240 channels 40  sectors 256 strips each 10240 channels Have increased number of strips by factor of 2 using ’128 ch VA-prime’ PA chip at practically same cost => average occupancy <1 for most strips! x 2 1 1 1 Si-1 inner Si-3Si-1 outer

22. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk22 Background from Secondaries Si1 outer Si1 inner Si2 inner Si3 Primaries Beam pipe ITS T0,V0,Abs, frames

23. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk23 Reconstruction of ’true’ multiplicity 10 HIJING events 1 HIJING event Primaries+secondaries Primaries Input dist and reconstructed HijingGeant= R * Hijing R = R(  ) response matrix

24. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk24 Iterative convolution of trial spectrum O = R * TrueSpec O(0)= R(0)* H TrueSpec(1)=O/O(1)*H O(1)= R(1)* TrueSpec(1) …Continue until O(n)  O Test of flat input distribution

25. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk25 Si-FMD timetable (1) AFRONT END (FE) READ OUT ELECTRONICSCompleted 1Demonstrate functionality of conceptual layout of FEE (Viking PA chip, control system, interface to ALTRO test board) August 2003 2Final choice of VA pre-ampl. chip. RO test 3Test FEE system coupled to sample Si detector. Source and electron beam tests. 4Design, construction and test of prototype FMD digitizer card (FMDD), RO test with ’mini’ FMD-RCU 5Full Si detector element + electronics chain RO with realistic RCU and DDL link to DAQ. June 1, 2004 BMECHANICS AND INTEGRATIONCompleted 1Full scale model manufactured (Si1)February 1, 2003 2Cabling and Cooling issues resolvedJune 1, 2003 3Full integration sequence decidedJune 1, 2003

26. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk26 Si-FMD timetable (2) C.SILICON DETECTORCompleted by 1Complete market surveyMay, 2003 2Define final specsOctober 2003 3Place order for prototype with industryNovember 2003 4Delivery Si-wafer prototypeFebruary 2004 5Start production of Si-hybrid FEE cardDecember 2003 6Delivery prototype hybridMarch 2004 7Si prototype test with FEE and BEE test RO setupApril 2004 8Place final order for Si with industryOctober 2004 Pre-assembly test July-Nov 2004 Construction, assembly, test at RHIC 2005 Installation June-Sept 2006

27. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk27 Si-FMD, TO,VO TDR time table. oFair amount of written material exists already (T0 100 pgs, Si-FMD 50 pgs, V0 20 pgs) oApril 15. Collect first detector chapters. oJune ’03. Editorial meeting. 1rst draft. oSummer ’03 Si-FMD electronics chain test. oJune ’03 T0 test beam oAugust ’03 V0 test beam oTDR writing: fall 2003

28. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk28 Techical Design Report Alice collab list. (5pgs) Summary of contents (2pgs) Table of contents. List of tables and figs.(4pgs) Color pictures of selected det. elements etc. (6pgs) 1. Physics objectives and design considerations T0, V0, Si-FMD trigger, timing, on-line mult, off-line mult, fluct, bgd rejection, overall performance, coverage etc...(10 pgs) 2. Design objectives, mechanical structure, Integration T0, V0, Si-FMD mounting, tolerances, clearances, inst. seq., cooling, cabling... (10pgs) 3. T0 (40 pgs) 4. V0 (40 pgs) 5. Si-FMD (40 pgs) 6. Installation, slow control, DAQ, safety. (10 pgs) 7. Organization(5 pgs) Group org., construction, installation, cost 8. References. (4pgs) 9. Index(2 pgs) (approx. 180 pgs)

29. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk29 Tasks and decisions for Weekly meetings (1) 1) Si sensors: - define final specs of sensor properties - negotiate price again with Hamamatsu and Micron - choose company - order prototype 2) Voltage supplies - define Voltage requirements (Volt, current, remote control and DCS) - investigate market (check out ITS or other Si systems in ALICE) 3) Bonding - decide on bonding strategy (CERN or other) - make arrangement with bonder 4) FEE-preamplifier card. - define final specs of FEE hybrid card - define interface to ALTRO -digitizer card and other slow controls. - define strategy: home built hybrid card with VA-prime from IDEAS or design and production by IDEAS and production for card? -updated cost estimate for industrial design and production (IDEAS)

30. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk30 Tasks and decisions for Weekly meetings(2) 5) Digitizer card (ALTRO board) -define interface to FEE and RCU - define necessary modifications to standard ALTRO boards 6) RCU card. - define interface to digitizer card (ALTRO board) - define necesary modifications to RCU 7) DDL and connection to DAQ -define modifications needed, if any 8) cabling and services, cooling - define cable types and length. - define connectors - define own cooling needs - define placement of cards/DDL etc in ALICE 9) Mechanical - define mechanical mounts for Si1, Si2, Si3. 10) Slow Control and DAQ communication - define tasks to be done -collect information and establish contact with DCS and DAQ groups.

31. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk31 Extra’s

32. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk32 Front end electronics REQUIREMENTS: Adapted for 5-25pF capacitance (300  m Si, 0.5 cm2: 25pF, 1MIP: 22.400 e-) Dynamic range: 0-20 MIPS Radiation hardness: >200kRad Peaking time: 1-2  s Low noise (good S/N) High integration Sample/hold and serial read- out, 10 MHz clock Moderate power consumption Simple slow controls and power reg. Affordable cost VA1 prime 2 (Viking-IDEAS): Input capacitance: < 30 pF 0-20 MIPs >1MRad (0.35  m tech.) 1-3  s 475 e- at 25 pF => S/N 20:1 128 10 Mhz clock 1.3 mW/ch Test system available OK

33. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk33 Multiplicity resolution

34. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk34 Reconstructed multiplicity. Average and width Background Subtracted All hits reconstructed  1.7  3.4

35. ALICE Si-FMD 10/09 2003Jens Jørgen Gaardhøje, NBI, gardhoje@nbi.dk35 Background  =2.4  =1.31  =1.73 Si3 Si2outer Si2inner Si1outer Si1inner Alla Maevskaia ALICE Week 9 September 2003