1. © 2009 Fakultas Teknologi Informasi Universitas Budi Luhur Jl. Ciledug Raya Petukangan Utara Jakarta Selatan 12260 Website: http://fti.bl.ac.id Email: sekretariat_fti@bl.ac.id Arsitektur Komputer Pertemuan – 15 Pemrosesan Paralel

2. Next Generation Network

7. Pemrosesan Paralel Multiple Processor Organization 1. Single instruction, single data stream - SISD 2. Single instruction, multiple data stream -SIMD 3. Multiple instruction, single data stream - MISD 4. Multiple instruction, multiple data stream- MIMD SISD 1. Single processor 2. Single instruction stream 3. Data stored in single memory 4. Uni-processor

8. Pemrosesan Paralel SIMD 1. Single machine instruction 2. Controls simultaneous execution 3. Number of processing elements 4. Lockstep basis 5. Each processing element has associated data memory 6. Each instruction executed on different set of data by different processors 7. Vector and array processors MISD 1. Sequence of data 2. Transmitted to set of processors 3. Each processor executes different instruction sequence 4. Never been implemented

9. Pemrosesan Paralel MIMD 1. Set of processors 2. Simultaneously execute different instruction sequences 3. Different sets of data 4. SMPs, clusters and NUMA systems

10. Pemrosesan Paralel Taxonomy of Parallel Processor Architectures

11. Pemrosesan Paralel MIMD - Overview General purpose processors Each can process all instructions necessary Further classified by method of processor communication Tightly Coupled - SMP Processors share memory Communicate via that shared memory Symmetric Multiprocessor (SMP) Share single memory or pool Shared bus to access memory Memory access time to given area of memory is approximately the same for each processor

12. Pemrosesan Paralel Tightly Coupled - NUMA Nonuniform memory access Access times to different regions of memroy may differ Loosely Coupled - Clusters Collection of independent uniprocessors or SMPs Interconnected to form a cluster Communication via fixed path or network connections

13. Pemrosesan Paralel Parallel Organizations - SISD

14. Pemrosesan Paralel Parallel Organizations - SIMD

15. Pemrosesan Paralel Parallel Organizations - MIMD Shared Memory

16. Pemrosesan Paralel Parallel Organizations - MIMD Distributed Memory

17. Pemrosesan Paralel Symmetric Multiprocessors A stand alone computer with the following characteristics Two or more similar processors of comparable capacity Processors share same memory and I/O Processors are connected by a bus or other internal connection Memory access time is approximately the same for each processor All processors share access to I/O Either through same channels or different channels giving paths to same devices All processors can perform the same functions (hence symmetric) System controlled by integrated operating system providing interaction between processors Interaction at job, task, file and data element levels

18. Pemrosesan Paralel Multiprogramming and Multiprocessing

19. Pemrosesan Paralel SMP Advantages 1. Performance: If some work can be done in parallel 2. Availability: Since all processors can perform the same functions, failure of a single processor does not halt the system 3. Incremental growth User can enhance performance by adding additional processors 4. Scaling 5. Vendors can offer range of products based on number of processors

20. Pemrosesan Paralel Block Diagram of Tightly Coupled Multiprocessor

21. Pemrosesan Paralel Organization Classification Time shared or common bus Multiport memory Central control unit Time Shared Bus Simplest form Structure and interface similar to single processor system Following features provided Addressing - distinguish modules on bus Arbitration - any module can be temporary master Time sharing - if one module has the bus, others must wait and may have to suspend Now have multiple processors as well as multiple I/O modules

22. Pemrosesan Paralel Symmetric Multiprocessor Organization

23. Pemrosesan Paralel Time Share Bus - Advantages Simplicity Flexibility Reliability Time Share Bus - Disadvantage Performance limited by bus cycle time Each processor should have local cache Reduce number of bus accesses Leads to problems with cache coherence Solved in hardware - see later