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Toshiba America Electronic Components, Inc. November 2003
Chip Enable Don’t Care NAND – Enabling Higher Performance, High Density NAND Flash Memory for Cellular Handset Applications Toshiba America Electronic Components, Inc. November 2003 Engineers of today’s feature-rich cell phones are finding multiple design challenges. To support these auxiliary and multimedia processing capabilities, they need a memory subsystem that is higher density and higher performance and ideally, lower cost. They also need a flexible solution that can accommodate low, mid and high-end configurations without major changes to the overall phone design. Today I’m going to speak with you about: Memory density trends in cell phones Memory requirements in next-generation cell phones Identify the different memory architectures The trade-offs with each and advantages by application How packaging innovations are important design considerations And tips for selecting the optimal memory subsystem for a specific application
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Chip Enabled “Don’t Care” NAND
Modified NAND Flash for easier integration in cell phones or other CE devices with complex memory subsystems. Targeted to address growing file storage requirements in cell phones Conventional NAND flash requires that the chip enable signal line be asserted low during the entire read cycle which prevents the processor from communicating with other devices on the same bus Chip Enable “Don’t Care” NAND flash allows the microprocessor to communicate with other devices on the bus such as SRAM, PSRAM or NOR flash while the NAND retrieves the information requested. Enables easier integration of NAND with NOR, SRAM and PSRAM in a system Initially available in 128Mb (TC581282AXB) and 256Mb (TC582562AXB) densities (.16 micron). New part numbers after die shrink to 0.13 micron in Q are TC58DDM82A1 (256Mb, 1.8V core and I/O) and TC58DDM82A1 (256Mb, dual power 2.5V to 3.6V for VCC and 1.65V to 1.85V for VCCQ). CEDC feature also now available in large block NAND in densities of 1Gb and 2Gb
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MCP Memory Subsystem Trend
Conventional “Talk-only” Cell phones used NOR + SRAM for code storage, backup and data storage memory requirements As cell phone applications have increased, the need for increased data storage for music, photo and data storage, as well as additional software application storage has made NAND Flash more attractive because of its faster program and erase times, higher density and smaller cell size. Chip Enable Don’t Care NAND makes NAND flash much easier to combine with NOR and other types of memory in memory subsystems (or multi-chip packages) with multiple types of memory CEDC NAND can be used in conventional cell phone architectures which combine NOR+SRAM+NAND or in newer NAND + low power SDRAM architectures. NOR+SRAM+NAND MCP solutions are rapidly gaining in acceptance among cell phone manufacturers
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NAND Flash Read Function Options
Type-1 (TSOP Package) Sequential Read /CE A Sequential Read (1) (00H) 0 527 /WE /RE R/B N Busy Data Output M I/O 00H Sequential Read Start-address input Type-2 (BGA/MCP Package) Chip Enable Don’t Care /CE don’t care No Sequential Read /CE Cell array Select page N M Figure 3. Read mode (1) operation 527 /WE /RE Data OutputにCE Clockを追加 ;020903 R/B N Busy Data Output M I/O 00H Start-address input Next Add. Input
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Memory Requirements for Cellular Phones
64M-128M Large Density High Speed Low Cost Low Power RAM Movie / Music Buffer Working Area PSRAM LP SDRAM 16M-32M 8M-16M 8M-16M Data Backup 8M-16M Low Power LP-SRAM 4M-8M MCP Talk only Browse phone G 16M 32M-64M 64M-128M 128M-256M High Speed Boot & Basic Program NOR Cellular phone memory requirements have become increasingly complex to support the additional features and applications that are now included. Cell phones have evolved from talk-only phones that needed only 4 – 8 Mb of low-power SRAM for data storage with 16Mb of NOR for code storage. Now, more complex phones need 8Mb to 16Mb of low-power SRAM for data backup, 32Mb to 128Mb Pseudo-SRAM (PSRAM) for program/movie/music working area; 128Mb to 256Mb high speed NOR for bootable code storage on basic phone programs, and 128Mb to 256Mb or more additional memory, often NAND Flash, for application software and storage. NAND flash is becoming popular because it is offered at a much lower cost-per-bit and with much higher Data Write/Erase performance. Recently cell phone designs have started using NAND flash plus low-power SDRAM combinations that enable a low-cost, high-capacity and high-performance solution. 128M-512M Large Density Low Cost High Speed program Flash Movie / Music App. Soft Storage NAND
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Application Trend and Onboard Memory Size
This is the trend of cell phone features in Japanese cell phone carrier. The rate at which designers are opting to add multiple applications is also growing at a much faster rate. A cellular phone with multimedia and digital camera functionality will need upwards of 144Mb of RAM with 512Mb of Flash memory. What also compounds and impacts memory capacity is the growing number of applications that cellular subscribers are demanding. Initial auxiliary applications such as and web browsing are being replaced by JAVA applications for downloading or more complex multimedia functions for movie, camera and music playback. As you can see from the trend line on the right side, the number of new phones that include digital camera capability is expected to increase rapidly over the next year or two. Memory size is increased by diversity of application .
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Multi-Chip Package for Mobile Phone
Demand from Mobile Phone Market MCP Solution Low cost solution Embedded High-Density NAND (128M/256M/512M +) High-Density Pseudo SRAM (32M/64M/128M) Demand of large density RAM and Flash. Increase of various application High-speed requirement for execution of application software (PSRAM/NOR) + High-Speed Function (PSRAM/NOR) 8Page Mode: 25ns→18ns Burst Mode 15ns Tradeoffs in density, speed, cost and power make combinations of several different types of memory desirable for cell phones. To address the various requirements, semi-custom combinations of two, three and four types of memory, packaged in a compact multi-chip package are needed to meet the demands for next-generation, multi-functioning phones. Multi-chip packages combine a complete, complex memory subsystem in a single, small component
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Architectures for next generation phones
Conventional solution Code : NOR Work : Pseudo-SRAM Data : NAND Backup : SRAM (in Japanese market) with burst mode Cost oriented solution Code & Data : NAND Work : LP-SDRAM with shadowing architecture The conventional memory architecture for today’s multi-function cellular phones typically uses NOR Flash for code storage, PSRAM for work space, NAND Flash for data storage and in some markets, SRAM for backup. Today, designers build upon the conventional cell phone memory architecture by increasing density of the NOR and PSRAM, and adding NAND Flash for data storage. And memory vendors have started to support Burst NOR and Burst PSRAM to improve performance of system. A newer approach well suited to 3G phones with advanced features used higher density, lower cost NAND with low power SDRAM in a shadowing architecture to provide a cost effective solution that can offer performance advantages due to the faster bus speed of the SDRAM.
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Mobile MCP Memory Trend
> 90% Camera Phones 2001 < 10% Camera Phones MP/Y SDRAM+NAND Production volume NAND+NOR+RAM NOR+RAM ・新たなMCPとしてSDRAM+NANDのMCPが03年より現れ、シャドウイングに適したソフトウェアが普及するに従って、 05年:8%、06年:20%、07年:37%と増加 ・NANDの搭載比率は05年には半数超えの57%、その後も増加。 ・東芝が売りとする多種・多段のメモリ構成の従来MCPは新MCPの存在とともに減少傾向ではあるが、07年でも 63%は残る。しかし、昨今の高性能化でPSRAM/NORのBurst機能は必要。 CY From 2003, NAND becoming popular in Europe and US (already popular in Asia) driven by storage requirements Source: Toshiba Internal Data/Projections
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Trend of Multi-Chip Package
more 7Chip over 5/6Chip St-MCP 1.6 1.6 9x12 3/4Chip St-MCP (NOR+NOR+SRAM+PSRAM) Stacked MCP 9x12 1.4 9x12 1.4 9 x 12 (SRAM+NOR) (NAND+NOR+PSRAM) 9x12 1.4 (4MS+32MF) 9x12 1.4 3Chip Package Area 0.8mm pitch 9x12 (16MS+64MF) Small 69 balls (Actual 56balls) 9x12 1.2 1.2 7x10 4Chip 1.4 7x10 3Chip 1.2 7 x 10 Small form factor Packaging advances today make it possible to create MCPs that stack up to 6 chips with different memory types into a single BGA package. 7x10 1.2 (8/4MS+64/32MF) 2000 2001 2002 2003 2004 CY
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5-chip Stacked-MCP Technology
TOSHIBA 5Chip St-MCP Chip5 Chip4 Chip3 Chip2 Chip1 1.6mm Max WIRE BOND PKG SIZE 9x12 7x10 Chip1 Chip2 Chip3 Chip4 Chip5 Innovations in miniaturization and thinner packages, combined with die shrinks have made this stacking technology possible. Toshiba uses a revolutionary new wire bond technique that further aids in stacking multiple chips. As handsets continue to shrink, MCPs are a necessity to integrate a complete, complex memory subsystem into a single small package.
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NAND / NOR Characteristics
3V, 1.8V x8/x16 50ns(serial access cycle) 25ms(random access) 200ms/512Byte 2ms/Block (16KB) 33.6ms / 64KB (x8) ~ 1Gbit NOR ~ 128Mbit 3V, 1.8V x8/x16 70ns(30pF, 2.3V) 65ns(30pF, 2.7V) 8ms/Byte 4.1ms/512Byte 700ms/Block 1.23s/Block (main:64KB) Capacity Power Supply I/O Access Time Program Speed (typ.) Erase Speed(typ.) Prog+Erase(typ.) This slide compares the major characteristics of NAND and NOR. NAND flash is currently available in densities 8 times greater than NOR. NAND also offers much faster programming and erase times, a small block size and requires less space because of its small cell size. On the other hand, NOR flash offers a slight advantage in random access times, because NOR Flash has a fully random access interface. But data in system, application program, image data and so on, usually is sizable, then sequential read of NAND Flash with 25 micro seconds initial delay, is enough for system’s requirement. And a difference in combined programming and erase time of 33 milliseconds for NAND and over 1 second for NOR is large enough to be detected by the user.
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4F2 10F2 NAND vs. NOR - Cell Structure NAND NOR Cell Array Layout
2F 4F2 NAND Source line Word line Unit Cell NOR Bit line Word line Contact Cell Array Unit Cell Source line 5F 2F Layout One of the most important characteristics of memory in a consumer electronics application is the bit cost. In the case of a semiconductor memory, the bit cost is dependent on the memory cell area per bit. Since the cell area of NAND Flash is smaller than the cell area of NOR Flash, NAND Flash offers the potential to be less expensive than NOR Flash. NOR Flash achieves random access by connecting the memory cells to the bit lines in parallel. Cross- section Cell size 10F2
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Performance comparison
Read Program NAND2LC NAND2LC 27MB/s 8.3MB/s NAND4LC 20.5MB/s Fast NAND4LC 1.7MB/s Fast NOR 2LC 55.2MB/s NOR 2LC 0.15MB/s NOR 4LC 50.0MB/s NOR 4LC 0.145MB/s Erase Slow 1.5ms 2ms 2s NOR 2LC 1.2s 4LC NAND2LC NAND4LC
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Performance comparison
NAND 2LC NAND 4LC NOR 2LC NOR 4LC 55.2MB/s Read 27MB/s 20.5MB/s 50.MB/s 25us+50nsx1056 for 2k bytes 50us+50nsx1056 for 2k bytes 80ns+30nsx7 for 16 bytes 85ns+25nsx3 for 8 bytes Prog. 8.3MB/s 1.7MB/s 0.15MB/s 0.145MB/s 50nsx µs for 2k bytes 50nsx ms for 2k bytes 107µs for 16 bytes 440µs for 64 bytes Erase 1.5ms 2ms 2s 1.2s 128 Kbytes 128 Kbytes 64 Kbytes 128 Kbytes
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Summary Memory requirements in high-end cell phones have increased dramatically to support new applications Different types of memory are best suited for different applications Code storage Working memory File and additional application storage Multi-chip packages (MCP) enable complex memory subsystems in a single component Traditional NOR +SRAM memory solutions for cell phones are being replaced by NOR+PSRAM+NAND and other combinations of multiple memories One newer low-cost alternative is NAND + Low Power SDRAM Chip Enable Don’t Care NAND Flash makes integration of NAND with other memory types much easier. In summary, the market for high-end cell phones has increased and so have the memory requirements to support new features and applications. Tradeoffs in density, speed, cost and power make combinations of different types of memory necessary for code storage, working memory and file and additional application storage. Because space is at a premium with the shrinking of the handset, multi-chip packages enable the creation of a complex memory subsystem in a single component. To save space and cost, traditional NOR and SRAM solutions are being replaced by NOR, Pseudo SRAM and NAND as well as other combinations that suit specific applications. For higher performance that supports many additional features, a newer low-cost alternative is NAND plus Low Power SDRAM. When selecting the optimal configuration for a cell phone memory subsystem, designers must evaluate how to balance the tradeoffs in cost, performance, power consumption and density to best fit the requirements of a specific design.
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