1. CS/COE0447 Computer Organization & Assembly Language
Chapter 2 Part 1

2. Topics to cover in Chapter 2
MIPS operations and operands
MIPS registers
Memory view
Instruction encoding
Arithmetic operations
Logic operations
Memory transfer operations

3. MIPS Operations/Operands
“Operation” (instruction)
“Operand”
MIPS operations
Arithmetic operations (integer/floating-point) (add, sub,…)
Logical operations (and, or,…)
Shift operations (shift a certain number of bits to the left or right)
Compare operations (do something if one operand is less than another,…)
Load/stores to transfer data from/to memory
Branch/jump operations
System control operations/coprocessor operations
MIPS operands
General-purpose registers
Fixed registers, e.g., HI/LO registers
Memory location
Immediate value

4. MIPS Arithmetic
rd rs rt
<op> <rdestination> <rsource1> <rsource2>
All arithmetic instructions have 3 operands
Operand order is fixed: destination first
32 registers (page 2 of green card)
Examples
add $t0, $s0, $s2 # $t0 = $s0 + $s2
sub $s0, $t0, $t1 # $s0 = $t0 – $t1

5. MIPS Registers $zero r0 r16 $s0 HI $at r1 r17 $s1 LO $v0 r2 r18 $s2
32 bits
32 bits
32 bits
$zero r0
r16
$s0 HI
$at r1
r17
$s1 LO
$v0 r2
r18
$s2
$v1 r3
r19
$s3
$a0 r4
r20
$s4
$a1 r5
r21
$s5
$a2 r6
r22
$s6
$a3 r7
r23
$s7
$t0 r8
r24
$t8
$t1 r9
r25
$t9
$t2
r10
r26
$k0
$t3
r11
r27
$k1
$t4
r12
r28
$gp
$t5
r13
r29
$sp
$t6
r14
r30
$fp
$t7
r15
r31
$ra PC
General-Purpose Registers
Special-Purpose Registers

6. General-Purpose Registers
GPR: all can be used as operands in instructions
Still, conventions and limitations exist to keep GPRs from being used arbitrarily
r0, termed $zero, always has a value “0”
r31, termed $ra (return address), is reserved for subroutine call/return
Etc. (we’ll see otherc conventsion/limitations later)
Register usage and related software conventions are summarized in “application binary interface” (ABI), which is important when writing system software such as an assembler and a compiler

7. Instruction Encoding Instructions are encoded in binary numbers
Assembler translates assembly programs into binary numbers
Machine decodes binary numbers to figure out what the instruction is
MIPS has “fixed” 32-bit instruction encoding
MIPS has several instruction formats
R-format: arithmetic instructions
I-format: transfer/branch/immediate format
J-format: jump instruction format
(FI/FR-format: floating-point instruction format)(later chapter)

8. MIPS Instruction Formats
Name
Fields
Comments
6 bits
5 bits
All MIPS instructions 32 bits
R-format op rs rt rd
shamt
funct
Arithmetic/logic instruction format
I-format
address/immediate
Transfer, branch, immediate format
J-format
target address
Jump instruction format

9. R-Format Instructions
Define “fields” of the following number of bits each: = 32 6 5
For simplicity, each field has a name:
opcode rs rt rd
funct
shamt
For shift instructions:
“shift amount”

10. R-Format Example MIPS Instruction:
add $8,$9,$10
Decimal number per field representation:
Binary number per field representation:
hex representation:
decimal representation:
On Green Card: Format in column 1, opcodes in column 3
(Let’s look and then come back)

11. M I P S Reference Data: CORE INSTRUCTION SET
NAME
MNE-MON-IC
FOR-MAT
OPERATION (in Verilog)
OPCODE/ FUNCT (hex)
Add
add R
R[rd] = R[rs] + R[rt] (1)
0 / 20hex
Add Immediate
addi I
R[rt] = R[rs] + SignExtImm (1)(2)
8hex
Branch On Equal
beq
if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4)
4hex
(1) May cause overflow exception
(2) SignExtImm = { 16{immediate[15]}, immediate }
(3) ZeroExtImm = { 16{1b’0}, immediate }
(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}
Later

12. R-Format Instructions (REMINDER)
Define “fields” of the following number of bits each: = 32 6 5
For simplicity, each field has a name:
opcode rs rt rd
funct
shamt

13. R-Format Example MIPS Instruction: Now let’s fill this in
add $8,$9,$10
Decimal number per field representation:
Binary number per field representation:
Now let’s fill this in

14. R-Format Example MIPS Instruction: 9 10 8 32 000000 01001 01010 01000
add $8,$9,$10
Decimal number per field representation: 9 10 8 32
Binary number per field representation:
hex
000000
01001
01010
01000
100000
00000
hex representation: A 4020hex
decimal representation: ,546,144ten

15. I-Format Instructions
Define “fields” of the following number of bits each: = 32 6 5 5 16
For simplicity, each field has a name:
opcode rs rt
immediate
Let’s do an example using addi

16. M I P S Reference Data: CORE INSTRUCTION SET
NAME
MNE-MON-IC
FOR-MAT
OPERATION (in Verilog)
OPCODE/ FUNCT (hex)
Add
add R
R[rd] = R[rs] + R[rt] (1)
0 / 20hex
Add Immediate
addi I
R[rt] = R[rs] + SignExtImm (1)(2)
8hex
Branch On Equal
beq
if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4)
4hex
(1) May cause overflow exception
(2) SignExtImm = { 16{immediate[15]}, immediate }
(3) ZeroExtImm = { 16{1b’0}, immediate }
(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}

17. I-Format Example MIPS Instruction: addi $8,$9,7
Decimal number per field representation:
Binary number per field representation:

18. I-Format Example MIPS Instruction: 001000 01001 01000 0000000000000111
addi $8,$9,7
Decimal number per field representation: 8 9 8 7
Binary number per field representation:
hex
hex representation: 0x

19. M I P S Reference Data: CORE INSTRUCTION SET
NAME
MNE-MON-IC
FOR-MAT
OPERATION (in Verilog)
OPCODE/ FUNCT (hex)
Add
add R
R[rd] = R[rs] + R[rt] (1)
0 / 20hex
Add Immediate
addi I
R[rt] = R[rs] + SignExtImm (1)(2)
8hex
Branch On Equal
beq
if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4)
4hex
(1) May cause overflow exception
(2) SignExtImm = { 16{immediate[15]}, immediate }
(3) ZeroExtImm = { 16{1b’0}, immediate }
(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}

20. Executing the addi instruction A
addi $8,$9,7 $8 $9 0x
Suppose 
Immediate = 0x0007 (16 bits; 4 hex digits)
SignExtImm = 0x (32 bits; 8 hex digits)
This will be more interesting when we
get to negative numbers.

21. Exercise Which instruction has same representation as 35ten?
A. add $0, $0, $0
B. subu $s0,$s0,$s0
C. lw $0, 0($0)
D. addi $0, $0, 35
E.  subu $0, $0, $0
F. Trick question! Instructions are not numbers.
Use Green Card to Answer
1 PERSON VOTE: Pink: 40%, Reed: 30%, Yellow: 20%, Blue: 20%
Afterwards: Pink 90%

22. Exercise Which instruction has same representation as 35ten? 32 16 35
A. add $0, $0, $0
B. subu $s0,$s0,$s0
C. lw $0, 0($0)
D. addi $0, $0, 35
E.  subu $0, $0, $0
F. Trick question! Instructions are not numbers.
Registers numbers and names: 0: $0, 8: $t0, 9:$t1, …,16: $s0, 17: $s1, …,
Opcodes and function fields
add: opcode = 0, function field = 32
subu: opcode = 0, function field = 35
addi: opcode = 8
lw: opcode = 35 35 32 8 16
1 PERSON VOTE: Pink: 40%, Reed: 30%, Yellow: 20%, Blue: 20%
Afterwards: Pink 90%

23. Which instruction bit pattern = number 35?
A. add $0, $0, $0
B. subu $s0,$s0,$s0
C. lw $0, 0($0)
D. addi $0, $0, 35
E.  subu $0, $0, $0
F.   35 32 8 16

24. Logic instruction format
Logic Instructions
Name
Fields
Comments
R-format op rs rt rd
shamt
funct
Logic instruction format
Bit-wise logic operations
<op> <rdestination> <rsource1> <rsource2>
Examples
and $t0, $s0, $s2 # $t0 = $s0 ^ $s2
or $s0, $t0, $t1 # $s0 = $t0 | $t1
nor $s0, $t0, $t1 # $s0 = ~($t0 | $t1)
xor $s0, $t0, $t1 # $s0 = $t0 ^ $t1

25. Logic Instructions: Example
.text
addi $t0,$0,0x32
addi $t1,$0,0x777
and $t2,$t1,$t0
Answer in class; also, replace and by or
Next: andi and ori

26. Andi and Ori andi I R[rt] & ZeroExtImm (3)
lui I R[rt] = {immediate,16’b0}
(3) ZeroExtImm = {16{1’b0},immediate}
In Verilog:
4'b // a 4-bit binary number
16'h704f // a 16-bit hex number
1b‘ // a 1-bit binary number
.text
lui $t1,0x7F40
addi $t2,$t1,0x777
andi $t3,$t2,0x5555
In class

27. Long Immediates (review)
Sometimes we need a long immediate, e.g., 32 bits
MIPS requires that we use two instructions
lui $t0, 0xaa55
Then we get lower-order 16 bits
ori $t0, $t0, 0xcc33
$t0
$t0

28. Loading a memory address
.data places values in memory starting at 0x So, 32 bits are needed to specify a memory address.
Format I has a 16 bit field and Format J has a 26 bit field…neither is long enough.
la $t0,0x is a pseudo instruction – not implemented in the hardware
lui $1, la $t0,0x
ori $8,$1,8
lw $t1,0($t0)

29. A program Get sample1.asm from the schedule Load it into the simulator
Figure out the memory contents, labels
Trace through the code

30. .data # sample1.asm
a: .word 3,4
c: .word 5,6
.text
la $t0,c # address of c
la $t1,k # address of k
lw $s0,0($t0) # load c[0]
lw $s1,4($t1) # load k[1]
slt $s3,$s0,$s1
# if c[0] < k[1], $s3 = 1, else $s3 = 0
beq $s3,$0,notless
# if c[0] < k[1] swap their values
sw $s0,4($t1)
sw $s1,0($t0)
notless:
.data
k: word 0xf,0x11,0x12