1. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan1 The 8051 Family Microcontroller Chin-Shiuh Shieh http://bit.kuas.edu.tw/~csshieh Department of Electronic Engineering National Kaohsiung University of Applied Sciences, Taiwan

2. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan2 Microcontrollers Microprocessors, such as 8086 family, have only CCU and ALU in them. External RAM, ROM, and I/O are required. Microcontrollers, such as 8051 family, encompass CCU, ALU, RAM, ROM, and I/O in a single chip, also called single-chip. Microcontrollers have limited computational power, but their low-cost make them prevalent in consumer products and small-scale control systems.

3. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan3 Microcontrollers (cont) We adopt 8051 family microcontroller in our class for its general structure and manageable system complexity. A large number of manufactures offer different variants of 8051 family microcontroller.

4. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan4 ATMEL AT89C51 AT89C51 / AT89S51 is a popular member of the 8051 family microcontroller from ATMEL.

5. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan5 Features 8-bit CPU optimized for control applications 128 bytes of on-chip Data RAM, 4K bytes of on-chip Program Memory (Flash Memory/ROM) 64K Program Memory address space, 64K Data Memory address space

6. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan6 Features (cont) 32 bidirectional and individually addressable I/O lines Two 16-bit timer/counters Full duplex programmable UART 6-source/5-vector interrupt structure with two priority levels

7. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan7 Pin Configurations

8. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan8 Pin Configurations (cont) Vcc, GND: supply voltage (5V), ground XTAL1, XTAL2: crystal connections for system clock RST: reset input EA: External Access, EA=5V to enable internal ROM.

9. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan9 Pin Configurations (cont) Basic hardware configuration Power-On self reset

10. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan10 Pin Configurations (cont) P0.0~P0.7: Port 0, bidirectional bit- addressable with open drain P1.0~P1.7: Port 1, bidirectional bit- addressable with internal pull-ups P2.0~P2.7: Port 2, bidirectional bit- addressable with internal pull-ups P3.0~P3.7: Port 3, bidirectional bit- addressable with internal pull-ups

11. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan11 Pin Configurations (cont)

12. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan12 Pin Configurations (cont) MOV P2,#0Ah;Copy 0A 16 to P2 MOV P2,#08;Copy 08 to P2 MOV P2,#00110100b;Copy 34 16 to P2 SETB P2.0;Set P2.0 to “1” CLR P2.1;Clear P2.1 to “0” MOV A,P1;Copy P1 to A JB P3.2,LOOP;Jump to LOOP if P3.1 is “1”

13. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan13 Pin Configurations (cont) P0 is open-drain –SETBP0.0;P0.0 = high impedance –CLRP0.1;P0.1 = 0V P1, P2, and P3 have internal pull-ups –SETBP1.0;P1.0 = 5V –CLRP1.1;P1.1 = 0V

14. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan14 "MOV P2,A" will turn on LEDs on P2 whose corresponding bits in A is "0". Notice that I/O port source current is limited. If an I/O port is used for input, it's output latch must set to "1". For example, "MOV P1,#0FFh", then "MOV A,P1" will read P1 status into A. MOV P1,#0FFh MOV A,P1

15. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan15 P0 is open-drain. Pull-up resistor is required. "SETB P0.0" will turn on the relay and "CLR P0.0" will turn it off. For button applications, de-bounce circuitry and code is required (5RC=10mS~20mS).

16. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan16 ORG0000h LOOP: SETBP2.0 LCALLDELAY CLRP2.0 LCALLDELAY LJMPLOOP DELAY: MOVR0,#0FFh L1:MOVR1,#0FFh L2:DJNZR1,L2; Decrease and jump if not zero DJNZR0,L1 RET END

17. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan17 for(R0=255;R0>=0;R0--) for(R1=255;R1>=0;R1--) { }

18. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan18 For button applications, de-bounce circuitry and code is required (5RC=10mS~20mS).

19. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan19

20. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan20 Check Button CHECK_BUTTON: JBP3.2,CBRET ; Task for button pressed WAIT_BUTTON_RELEASE: JNB P3.2,WAIT_BUTTON_RELEASE CBRET:

21. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan21

22. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan22 Wait Button WAIT_BUTTON: JB P3.2,WAIT_BUTTON WAIT_RELEASE: JNB P3.2,WAIT_RELEASE RET

23. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan23 Pin Configurations

24. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan24 Pin Configurations (cont) Alternative Functions of Port 3

25. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan25 Polling I/O Interrupt-driven I/O –Interrupt Service Subroutine

26. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan26 Pin Configurations (cont) PSEN: Program Store Enable, read strobe for external program memory ALE: Address Latch Enable, for multiplexing AD0~AD7 A8~A15(P2.0~P2.7): high-byte address bus for external addressing AD0~AD7(P0.0~P0.7): multiplexed low- byte address bus and data bus for external addressing

27. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan27 Memory Organization Separation of program addressing space and data addressing space.

28. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan28 Program Memory

29. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan29 Data Memory

30. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan30 Internal Data Memory MOV 12h,#05h MOV A,3Ch MOV 0E0h,3Ch; MOV A,3Ch MOV 90h,#0Fh; MOV P1,#0Fh MOV A,R0 MOV 20h,#05h SETB 03h MOV A,20h; A==0D

31. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan31 Special Function Register Map

32. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan32 MOV SBUF,#’H’ ;== MOV SBUF,#48h MOV SBUF,#’e’

33. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan33 Special Function Register Map (cont)

34. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan34 Special Function Register Map (cont) MOV P2,#55h == MOV 0A0h,#55h SETB P1.0 CLR P1.0 SETB SBUF.1;Incorrect!

35. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan35 Special Function Register Map (cont) MOV SBUF,A = MOV 99h,0E0h MOV 99h,A

36. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan36 Special Function Registers A, (ACC): Accumulator –MOV A,#02h –ADD A,#03h; ADD B,R0 incorrect! –B: B Register –MUL AB MOV A,#03h MOV R0,#02h MUL AB; MUL AR0 Incorrect! –DIV AB SP: Stack Pointer DPTR(DPH,DPL): Data Pointer –MOV DPTR,#4000h –MOVX A,@DPTR –MOVX @DPTR,A

37. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan37 Special Function Registers (cont) P0: Port 0 P1: Port 1 P2: Port 2 P3: Port 3

38. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan38 Special Function Registers (cont) TH0: Timer/Counter 0 High Byte TL0: Timer/Counter 0 Low Byte TH1: Timer/Counter 1 High Byte TL1: Timer/Counter 1 Low Byte SBUF: Serial Data Buffer –MOV SBUF,A –MOV SBUF,#’H’;

39. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan39 Special Function Registers (cont) PSW: Program Status Word PCON: Power Control Register IE: Interrupt Enable Register IP: Interrupt Priority Register TCON: Timer/Counter Control Register TMOD: Timer/Counter Mode Control Register SCON: Serial Port Control Register

40. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan40 PSW: Program Status Word

41. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan41 PSW: Program Status Word (cont) SETB RS1 CLR RS0 MOV R0,#5Fh

42. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan42 PCON: Power Control Register

43. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan43 PCON: Power Control Register (cont) SETB SMOD; Incorrect MOVA,PCON ORLA,#10000000b MOVPCON,A CLR GF0; Incorrect MOV A,PCON ANL A,#11111011b MOV PCON,A

44. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan44 IE: Interrupt Enable Register ; Enable External Interrupt 0 with high priority SETB EX0 SETB EA SETB PX0

45. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan45 IP: Interrupt Priority Register

46. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan46 TCON: Timer/Counter Control Register

47. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan47 TMOD: Timer/Counter Mode Control Register

48. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan48 TMOD: Timer/Counter Mode Control Register (cont) TH1TL1 FD FF 8-bit Auto-reload mode MOV SBUF,A MOV SBUF,B

49. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan49 SCON: Serial Port Control Register

50. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan50 MOVSBUF,A MOVA,SBUF MOV SBUF,#’H’ MOV SBUF,#’e’ MOV SBUF,#’l’ MOV SBUF,#’o’

51. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan51 PC: Program Counter –16-bit register –Instruction fetching –Auto increase

52. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan52 Interrupt Mechanism

53. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan53 Pin Configurations

54. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan54

55. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan55 Pin Configurations

56. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan56 Interrupt Mechanism (cont)

57. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan57 Interrupt Mechanism (cont)

58. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan58 Addressing Mode Immediate: MOV A,#20h Register: MOV A,R0 Direct: MOV A,30h Indirect: MOV A,@R0 External Data Indirect: MOVX A,@DPTR Code Indirect: MOVC A,@A+DPTR

59. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan59 MOV DPTR,#0A05Ch MOVX A,@DPTR MOVX @DPTR,A

60. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan60 MOV A,#00h ADD A,00h ADD A,01h ADD A,02h … ADD A,09h

61. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan61 int x[10]; int sum; sum=0; sum=sum+x[0]; sum=sum+x[1]; sum=sum+x[2]; … sum=sum+x[9];

62. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan62 int x[10]; int sum; for(i=0;i<10;i++) –sum=sum+x[i];

63. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan63 MOVA,00h MOVR0,#09h LOOP: ADDA,@R0 DJNZR0,LOOP

64. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan64 int x[10],sum; sum=sum+x[0]; sum=sum+x[1]; sum=sum+x[2]; … sum=sum+x[9];

65. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan65 int x[10],sum,i; for(i=0i<10;i++) –sum=sum+x[i];

66. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan66 Instruction Set ASEM51 v1.3 –Assembler Directives ORG EQU Emulator 8051 V1.0 or JSIM-51

67. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan67 ADD vs. ADDC

68. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan68 JB bit, rel JNB bit, rel JC rel JNC rel JZ rel ; Jump if A==0 JNZ rel

69. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan69 ADD B,R0 ANL A,#00001111b MOV A,PCON ANL A,#01111111b MOV PCON,A

70. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan70 MOV A,00h ADD A,04h MOV 08h,A MOV A,01h ADDC A,05h MOV 09h,A

71. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan71 MOV R0,#10 LOOP: … DEC R0 CJNE R0,#00, LOOP

72. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan72 JB bit, rel JNB bit, rel JC rel JNC rel JZ rel JNZ rel JB bit, rel vs. JBC bit, rel

73. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan73 ? SP DA A JMP @A+DPTR POP direct PUSH direct XCHD A, @Ri

74. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan74 RL A RLC A

75. Autumn 2013C.-S. Shieh, EC, KUAS, Taiwan75