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Design of a Multimedia Extension for RISC Processor

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Presentation on theme: "Design of a Multimedia Extension for RISC Processor"— Presentation transcript:

1 Design of a Multimedia Extension for RISC Processor
NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER Design of a Multimedia Extension for RISC Processor Eduardo Jonathan Martínez Montes Prof. Marco Antonio Ramírez Salinas IPN-CIC MICROSE Lab

2 Adder-Substracter Saturated/Wrapped 8 bits
OUTLINE Adder Full adder Ripple carry adder Carry look ahead adder Best adder Adder-Substracter Saturated/Wrapped 8 bits Adder-Substracter Saturated/Wrapped 16 bits Multiplier Multiplier 8x8 Multiplier 16x16 Vector operations Over view Vector formats OB format OH format Prototype Instruction path Results IPN-CIC MICROSE Lab 2

3 A full adder is an arithmetic circuit that is used to add three bits.
Logic diagram Block diagram Boolean functions IPN-CIC MICROSE Lab 3

4 The carry propagation time is the major speed limiting factor.
ADDER Ripple Carry Adder (part 1) The carry propagation time is the major speed limiting factor. IPN-CIC MICROSE Lab 4

5 Ripple Carry Adder (part 2)
IPN-CIC MICROSE Lab 5

6 Features Resources: 35 LE Fmax: 208.90 MHz Size: 16 bits ADDER
Ripple Carry Adder (part 3) Features Resources: 35 LE Fmax: MHz Size: 16 bits IPN-CIC MICROSE Lab 6

7 ADDER Carry Look Ahead Adder (part 1) It improves speed by reducing the amount of time required to determine carry bits. IPN-CIC MICROSE Lab 7

8 Carry Look Ahead Adder (part 2)
IPN-CIC MICROSE Lab 8

9 Features Resources: 57 LE Fmax: 223.51 MHz Size: 16 bits ADDER
Carry Look Ahead Adder (part 3) Features Resources: 57 LE Fmax: MHz Size: 16 bits IPN-CIC MICROSE Lab 9

10 It is widely considered the fastest adder design possible.
Kogge Stone Adder (part 1) It is widely considered the fastest adder design possible. IPN-CIC MICROSE Lab 10

11 Black Cell Gray Cell ADDER Kogge Stone Adder (part 2) IPN-CIC
MICROSE Lab 11

12 Features Resources: 82 LE Fmax: 255.17 MHz Size: 16 bits ADDER
Kogge Stone Adder (part 3) Features Resources: 82 LE Fmax: MHz Size: 16 bits IPN-CIC MICROSE Lab 12

13 ADDER Best adder IPN-CIC MICROSE Lab 13

14 Features Operations: Adder, Substracter Arithmetic: Saturated, Wrapped
Adder-Substracter Saturated/Wrapped 8 bits Features Operations: Adder, Substracter Arithmetic: Saturated, Wrapped Size: 8 bits Unsigned Integer Resources: 59 LE Fmax: MHz IPN-CIC MICROSE Lab 14

15 Features Operations: Adder, Substracter Arithmetic: Saturated, Wrapped
Adder-Substracter Saturated/Wrapped 16 bits Features Operations: Adder, Substracter Arithmetic: Saturated, Wrapped Size: 16 bits Signed Integer Resources: 113 LE Fmax: MHz IPN-CIC MICROSE Lab 15

16 Features Operations: Multiplier Arithmetic: Saturated, Wrapped
Multiplier 8x8 Features Operations: Multiplier Arithmetic: Saturated, Wrapped Size: 8x8=16 bits Unsigned Integer Resources: 308 LE Fmax: MHz IPN-CIC MICROSE Lab 16

17 Features Operations: Multiplier Arithmetic: Saturated, Wrapped
Multiplier 16x16 Features Operations: Multiplier Arithmetic: Saturated, Wrapped Size: 16x16=32 bits Signed Integer Resources: 1,723 LE Fmax: MHz IPN-CIC MICROSE Lab 17

18 VECTOR OPERATIONS Over view Single Instruction Multiple Data, this architecture performs the same operation on multiple data elements in parallel. IPN-CIC MICROSE Lab 18

19 VECTOR OPERATIONS Over view (cont.) IPN-CIC MICROSE Lab 19

20 Accumulator contains 8 24 bits elements.
VECTOR FORMAT OB format Unsigned. 64 bits vector 8 elements each one 8 bits Accumulator contains 8 24 bits elements. IPN-CIC MICROSE Lab 20

21 4 elements each one 16-bits Accumulator contains 4 48-bits elements.
VECTOR FORMAT HB format Signed. 64 bits vector 4 elements each one 16-bits Accumulator contains 4 48-bits elements. IPN-CIC MICROSE Lab 21

22 PROTOTYPE Instruction path IPN-CIC MICROSE Lab 22

23 Features Resources: 8,449 LE Fmax: 176.27 MHz
PROTOTYPE Prototype Features Resources: 8,449 LE Fmax: MHz ADD, ADDL, ADDA SUB, SUBL, SUBA MUL, MULL, MULA LDC2, SDC2 No LPM IPN-CIC MICROSE Lab 23

24 ldc2 $v3, 0($0) # $v3 = $s0 let $s0=64'h0102030405060708
PROTOTYPE Results ldc2 $v3, 0($0) # $v3 = $s0 let $s0=64'h sdc2 $v3, 0($s0) # $s0 = $v3 ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0) # $s0 = $v3 ldc2 $v5, 0($0) # $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122 sdc2 $v5, 0($s0) # $s0 = $v3 IPN-CIC MICROSE Lab 24

25 ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB
PROTOTYPE Results (cont.) ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0) # $s0 = $v3 ldc2 $v5, 0($0) # $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122 sdc2 $v5, 0($s0) # $s0 = $v3 add.ob $v6,$v4,$v5 #$v6 = $v4+$v5 $V4 = 0A 0B 0C 0D 0E 0F AA BB + $V5 = AA BB CC DD EE FF 11 22 $V6 = B4 C6 D8 EA FC FF BB DD Saturated IPN-CIC MICROSE Lab 25

26 ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB
PROTOTYPE Results (cont.) ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0) # $s0 = $v3 ldc2 $v5, 0($0) # $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122 sdc2 $v5, 0($s0) # $s0 = $v3 add.ob $v7,$v4,$v5(0) #$v7 = $v4+$v5(0) $V = 0A 0B 0C 0D 0E 0F AA BB + $V5(0) = $V = 2C 2D 2E 2F CC DD IPN-CIC MICROSE Lab 26

27 ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB
PROTOTYPE Results (cont.) ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0) # $s0 = $v3 add.ob $v8,$v4,10 #$v8 = $v $V = 0A 0B 0C 0D 0E 0F AA BB + 0A 0A 0A 0A 0A 0A 0A 0A $V = B4 C5 IPN-CIC MICROSE Lab 27

28 ldc2 $v2, 0($0) # $v3 = $s0 let $s0=64'h0908070605040302
PROTOTYPE Results (cont.) ldc2 $v2, 0($0) # $v3 = $s0 let $s0=64'h sdc2 $v2, 0($s0) # $s0 = $v2 ldc2 $v3, 0($0) # $v3 = $s0 let $s0=64'h sdc2 $v3, 0($s0) # $s0 = $v3 mul.ob $v9,$v2,$v3 #$v9 = $v2*$v3 $V = X $V = $V = IPN-CIC MICROSE Lab 28

29 Q&A IPN-CIC MICROSE Lab 29

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