1. These slides incorporate figures from Digital Design
Principles and Practices, third edition, by John F.
Wakerly, Copyright 2000, and are used by permission. NO permission is given to re-use or publish these
figures, in either original or modified form, in printed,
electronic or any other format.

2. Slide Set 10
Sequential machines

3. Clocked synchronous state machines:
Mealy:
(next state)
Moore:
(next state)

4. Mealy machine with pipelined outputs
---resynchronized

5. Flip-flop characteristic equations:
D Q+ = D
D with enable Q+ = DEN + QEN’
JK Q+ = J Q’ + K’ Q
T Q+ = Q’
T with enable Q+ = Q’EN + Q EN’

6. Example: analysis with state machine (D flip-flops)
Goals:
Characterize as Mealy or Moore machine
Determine next-state as function of inputs and current state
Determine output as function of current state (Moore) or as function of current state and current inputs (Mealy)
Express as machine behavior as state/output table or as state diagram
Formulate English description of machine behavior

7. Q0+ = D0
Q1+ = D1
D0 = F (Q1, Q0, EN)
D1 = G (Q1, Q0, EN) EN
Q1 Q0 0 1 00 01 10 11
For Q1+: 1

8. Derive truth tables from diagram
next state: Q1+ Q0+ EN
S 0 1
A A B
B B C
C C D
D D A
next state: S+ EN
Q1 Q0 0 1
Rename states
00 => A
01 => B
10 => C
11 => D EN
Q1 Q0 0 1
00 00,0 01,0
01 01,0 10,0
10 10,0 11,0
11 11,0 00,1
next state: Q1+ Q0+
output (MAX) EN
Q1 Q0 0 1
A A,0 B,0
B B,0 C,0
C C,0 D,0
D D,0 A,1
next state: S+
output (MAX)

9. Equivalent state diagram
--- Mealy machine has outputs on transition arcs
English description:
Machine counts EN pulses mod 4,
raises MAX when count will achieve 0 mod 4 on next clock

10. Same analysis approach:
Remove input connection to output logic => Moore machine X
Note: MAX = 1 only
when Q1=Q0=1
Same analysis approach:
Determine next-state and output functions
Express as state/output table and/or as state diagram

11. State table: State diagram: next state: S+ and output (MAX) EN MAX
A A B 0
B B C 0
C C D 0
D D A 1
Moore machine
single output column
outputs in state circles
State diagram:
English description: Machine counts EN pulses mod 4, raises MAXS when
current count is 3 mod 4.

12. Can use complemented outputs to save inverters:

13. --- for Mealy (MAX) and Moore (MAXS) version
State transitions
--- for Mealy (MAX) and Moore (MAXS) version
Output tracking input in state D
independent of clock edge
Mealy machine behavior

14. To analyze a synchronous state machine:
Determine excitation equations for flip-flop inputs
Substitute into flip-flop characteristic equations to obtain transition equations
Construct transition table
Determine output equations
Add outputs to states (Moore) or state/input combinations (Mealy)
Name states and draw state diagram

15. Q1+ = D1 = Q2’Q0X + Q1X’ + Q2Q1 Q2+ = D2 = Q2Q0’ + Q0’X’Y
Q0+ = D0 = Q1’X + Q0X’ + Q2
Q1+ = D1 = Q2’Q0X + Q1X’ + Q2Q1
Q2+ = D2 = Q2Q0’ + Q0’X’Y
Another example:
Z1 = Q2Q1’ + Q0’
Z2 = Q2Q1 + Q2Q0’

16. State table (Moore machine)

17. State diagram note alternative conventions for arc labels
X alone means Y can be either 0 or 1
same as two arcs with 10 and 11
or a single arc with multiple labels 00
(10, 11) 01
State diagram

18. Example: JK flip-flops
characteristic equation: Q+ = JQ'+K'Q
Q0+ = J0Q0’ + K0’Q0
= XY’Q0’ + X’Y’Q0 +
X’Q1’Q0 + YQ1’Q0
Q1+ =   
J0 = XY’
K0 = XY’ + YQ1
J1 = XQ0 + Y
K1 = YQ0’ + XY’Q0
Z = XQ1Q0 + YQ1’Q0’

20. 00/0
10/0
(01,11)/1

21. Design example:

22. Establish tentative state transitions
Meaning S Z
Initial state INIT 0
... AB
Meaning S Z
Initial state INIT A0 A0 A1 A1 0
Got a 0 on A A
Got a 1 on A A
...

23. AB
Meaning S Z
Initial state INIT A0 A0 A1 A1 0
Got a 0 on A A0 OK OK A1 A1 0
Got a 1 on A A
Repeat on A OK 1
...

24. AB
Meaning S Z
Initial state INIT A0 A0 A1 A1 0
Got a 0 on A A0 OK OK A1 A1 0
Got a 1 on A A1 A0 A0 OK OK 0
Repeat on A OK 1
...

25. Initial state INIT A0 A0 A1 A1 0 Got a 0 on A A0 OK OK A1 A1 0
if two equal inputs are 0, want to stay in OK
else want to return to A0
if two equal inputs are 1, want to stay in OK
else want to return to A1 AB
Meaning S Z
Initial state INIT A0 A0 A1 A1 0
Got a 0 on A A0 OK OK A1 A1 0
Got a 1 on A A1 A0 A0 OK OK 0
Repeat on A OK ? OK OK ? 1
...

26. AB
Meaning S Z
Initial state INIT A0 A0 A1 A1 0
Got a 0 on A A0 OK0 OK0 A1 A1 0
Got a 1 on A A1 A0 A0 OK1 OK1 0
Equal, last 0 OK0 OK0 OK0 OK1 A1 1
Equal, last 1 OK

27. AB
Meaning S Z
Initial state INIT A0 A0 A1 A1 0
Got a 0 on A A0 OK0 OK0 A1 A1 0
Got a 1 on A A1 A0 A0 OK1 OK1 0
Equal, last 0 OK0 OK0 OK0 OK1 A1 1
Equal, last 1 OK1 A0 OK0 OK1 OK1 1

28. Test design on input scenarios

29. Assign bit patterns to the five statesAB
S Z
INIT A0 A0 A1 A1 0
A0 OK0 OK0 A1 A1 0
A1 A0 A0 OK1 OK1 0
OK0 OK0 OK0 OK1 A1 1
OK1 A0 OK0 OK1 OK1 1
first bit: initial or working
second bit: pending or pattern recognized
third bit: pending or recognized pattern with 0 or with 1
State Simple Decomposed One-hot Almost one-hot
INIT A A OK OK
Some alternatives

30. Transition/output table (decomposed assignment)
With D flip-flops, excitation table is identical to transition table
Have three combinational design problems for Q1+ = D1, Q2+ = D2, Q3+ = D3

31. Develop excitation equations
Assume unused states have next-state = 000
=> 9 NAND gates

32. Assume “don’t care” for transitions from unused states:
D2 = Q3’Q1A’ + Q3A + Q2B
D3 = A
=> 4 NANDS

34. Same example using ABEL
Note about reset inputs:
You always need a “power-on” reset input for a sequential circuit.
Previous example did not use synchronous reset because of manual-synthesis complexity.
Asynchronous reset is sometimes used (PR and CLR inputs of flip-flops).

35. Note definition of “extra” states.
State assignment
uses simple sequential binary patterns
Note definition of “extra” states.

36. “State Diagram”
This essentially mimics the state table.

37. Final touches
Good behavior for extra states state XTRA1: GOTO INIT; state XTRA2: GOTO INIT; state XTRA3: GOTO INIT;
Clock and output equations equations QSTATE.CLK = CLOCK; QSTATE.OE = 1; Z = (QSTATE == OK0) # (QSTATE == OK1);
Alternative state assignments are easy
Modify state definitions and possibly output pins and extra states.
Unspecified states go to 0,0,…0.

38. ABEL-derived excitation equations
Q3.FB ??
next slide
Equivalent to what was derived by hand, with the addition of the RESET input.

39. Qualified signals from flip-flops
.CLK or .C clock
.AR asynchronous clear
.AP asynchronous preset
.OE output enable
.Q direct output
.FB output after programmed inversion
.PIN output appearing on pin

40. Same example
use JK flip-flops
decomposed assignment AB
S Z
INIT A0 A0 A1 A1 0
A0 OK0 OK0 A1 A1 0
A1 A0 A0 OK1 OK1 0
OK0 OK0 OK0 OK1 A1 1
OK1 A0 OK0 OK1 OK1 1 AB
Q2 Q1 Q Z

41. Separately for each AB input,
add columns for excitations (Ji, Ki) for each flip-flop AB
Q2 Q1 Q J2 K2 J1 K1 J0 K0 Z
Q2 transitions 0 to 1
J2 K2 must command set or toggle
J2 K2 = 10 or 11, i.e., 1x 1x
Q1, Q0 hold 0
J1 K1, J0 K0 must command reset or hold
J1 K1, J0 K0 = 00 or 01, i.e., 0x 0x
Q2+ Q1+ Q0+

42. Add columns for excitations (Ji, Ki) for each flip-flopAB
Q2 Q1 Q J2 K2 J1 K1 J0 K0 Z
x 0x 0x 0
x0 1x 0x 0
x0 0x x1 0
x0 x0 0x 1
x0 x1 x1 1
Q2+ Q1+ Q0+
Transition JK command
0 => or 01 => 0x
0 => or 11 => 1x
1 => or 11 => x1
1 => or 10 => x0

43. Add columns for excitations (Ji, Ki) for each flip-flop
AB = 00
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 0x
x0 1x 0x
x0 0x x1
x0 x0 0x
x0 x1 x1
Q2 = 0: AB
01 x x x x
Q1 Q0 11 x x x x
10 x x x x
Q2 = 1:
00 x x x x
J2 = 1
AB = 01
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 0x
x0 1x 0x
x0 0x x1
x0 x0 0x
x0 x0 x1
AB = 11
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 1x
x0 0x 1x
x0 1x x0
x0 x0 1x
x0 x0 x0
Q2 = 0: AB
00 x x x x
01 x x x x
Q1 Q0 11 x x x x
10 x x x x
Q2 = 1:
Q1 Q
K2 = 0
AB = 10
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 1x
x0 0x 1x
x0 1x x0
x0 x1 1x
x0 x0 x0

44. Add columns for excitations (Ji, Ki) for each flip-flop
AB = 00
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 0x
x0 1x 0x
x0 0x x1
x0 x0 0x
x0 x1 x1
Q2 = 0: AB
01 x x x x
Q1 Q0 11 x x x x
10 x x x x
Q2 = 1:
J1 = Q0 • A + Q2 • Q0' • A'
AB = 01
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 0x
x0 1x 0x
x0 0x x1
x0 x0 0x
x0 x0 x1
AB = 11
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 1x
x0 0x 1x
x0 1x x0
x0 x0 1x
x0 x0 x0
Q2 = 0: AB
00 x x x x
01 x x x x
Q1 Q0 11 x x x x
10 x x x x
Q2 = 1:
Q1 Q
K1 = Q0 • A • B' + Q0' • A' • B'
AB = 10
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 1x
x0 0x 1x
x0 1x x0
x0 x1 1x
x0 x0 x0

45. Add columns for excitations (Ji, Ki) for each flip-flop
AB = 00
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 0x
x0 1x 0x
x0 0x x1
x0 x0 0x
x0 x1 x1
Q2 = 0: AB
01 x x x x
Q1 Q0 11 x x x x
10 x x x x
Q2 = 1:
Q1 Q
J0 = A
AB = 01
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 0x
x0 1x 0x
x0 0x x1
x0 x0 0x
x0 x0 x1
AB = 11
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 1x
x0 0x 1x
x0 1x x0
x0 x0 1x
x0 x0 x0
Q2 = 0: AB
00 x x x x
01 x x x x
Q1 Q0 11 x x x x
10 x x x x
Q2 = 1:
K0 = A'
AB = 10
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
x 0x 1x
x0 0x 1x
x0 1x x0
x0 x1 1x
x0 x0 x0

46. A B
Z = Q2 • Q1 Z
JK flip-flop
J Q
K Q'
CLR Q2 1
NAND-NAND
J = Q0 • A + Q2 • Q0' • A' J
K = Q0 • A • B' + Q0' • A' • B' K
JK flip-flop
J Q
K Q'
CLR Q1
JK flip-flop
J Q
K Q'
CLR Q0
initially GND
pull-up to PWR
after small time
interval
CLK