Presentation is loading. Please wait.

Presentation is loading. Please wait.

Lecture 16 PicoBlaze Instruction Set & Assembler Directives

Published byZack Leadingham Modified over 9 years ago

Similar presentations

Presentation on theme: "Lecture 16 PicoBlaze Instruction Set & Assembler Directives"— Presentation transcript:

1 Lecture 16 PicoBlaze Instruction Set & Assembler Directives
ECE 448 – FPGA and ASIC Design with VHDL

2 ECE 448 – FPGA and ASIC Design with VHDL
Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 15 PicoBlaze Assembly Code Development Recommended reading K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6) ECE 448 – FPGA and ASIC Design with VHDL

3 PicoBlaze-6 Programming Model
Bank B Bank A FFC FFD FFE FFF ECE 448 – FPGA and ASIC Design with VHDL

4 Syntax and Terminology
Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) s7 0xAB PORT(2) PORT((sa)) RAM(4) Value at register 7 Constant AB (in hex) Input value from port 2 Input value from the port specified by register a Value from RAM location 4

5 Addressing modes Immediate mode SUB s7, 0x07 s7 <= s7 – 0x07
s2 <= s2 + 0x08 + C Immediate mode SUB s7, 0x07 ADDC s2, 0x08 Direct mode ADD sa, sf IN s5, 0x2a sa <= sa + sf s5 <= PORT(0x2a) Indirect mode STORE s3, (sa) IN s9, (s2) RAM((sa)) <= s3 s9 <= PORT((s2))

6 PicoBlaze Development Environments
Xilinx KCPSM3/ 6 OpenPIC IDE Platform support Windows Windows XP, Windows 7 and 8 Assembler Command-line in DOS window Graphical Instruction Syntax KCPSM3/ 6 OpenPIC Instruction Set Simulator Facilities provided for VHDL simulation Graphical/ Interactive Simulator Breakpoints N/A Yes Register Viewer Memory Viewer

7 ECE 448 – FPGA and ASIC Design with VHDL
KCPSM6 Assembler Files KCPSM6.EXE ECE 448 – FPGA and ASIC Design with VHDL

8 Directives of Assembly Language
Function KCPSM3/ 6 Directive OpenPIC Directive Locating Code ADDRESS 3FF ORG 0x3FF Aliasing Register Names NAMEREG s5, myregname myregname EQU s5 Declaring Constants CONSTANT myconstant, 80 myconstant EQU 0x80 Naming the program ROM file Name using the same base filename as the assembler source file Specify the VHDL template file in the project settings under processor tab and compiler options Equating symbolic name for an I/O port ID N/A sw_port EQU 0x01 ; 8-bit switches sw_in EQU sf IN sw_in, sw_port ; read switch input data EQU s0 ; reg for tmp data led_port EQU 0x05 OUT data, led_port

9 Differences between Mnemonics of Instructions
KCPSM3/ 6 Mnemonic OpenPIC Mnemonic RETURN RET RETURN C RET C RETURN NC RET NC RETURN Z RET Z RETURN NZ RET NZ RETURNI ENABLE RETI ENABLE RETURNI DISABLE RETI DISABLE ENABLE INTERRUPT EINT DISABLE INTERRUPT DINT

10 Differences between Mnemonics of Instructions
ADDCY sX, sY ADDC sX, sY SUBCY sX, sY SUBC sX, sY INPUT sX, (sY) IN sX, (sY) INPUT sX, kk IN sX, kk OUTPUT sX, (sY) OUT sX, (sY) COMPARE sX, sY COMP sX, sY STORE sX, (sY) FETCH sX, (sY)

11 Differences between Programs

12 Basic Data Movement Instructions

13 Data Movement Instructions
C Z - - LOAD LOAD sX, sY sX <= sY LOAD sX, KK sX <= KK IMM, DIR

14 Logic Instructions & Bit Manipulation

15 Logic instructions C Z IMM, DIR IMM, DIR IMM, DIR AND AND sX, sY
sX <= sX and sY AND sX, KK sX <= sX and KK 2. OR OR sX, sY sX <= sX or sY OR sX, KK sX <= sX or KK 3. XOR XOR sX, sY sX <= sX xor sY XOR sX, KK sX <= sX xor KK IMM, DIR IMM, DIR IMM, DIR

16 Perform the following operations in the assembly language of PicoBlaze
Questions Perform the following operations in the assembly language of PicoBlaze Set the most significant bit of the register s0 to 1 Clear two middle bits of the register s1 Toggle the least significant bit of the register s2

17 Answers Set the most significant bit of the register s0 to 1
BIT7 EQU 0x80 OR s0, BIT7 Clear two middle bits of the register s1 BITS43C EQU 0xE7 AND s1, BITS43C Toggle the least significant bit of the register s2 BIT0 EQU 0x01 XOR s2, BIT0

18 Arithmetic Instructions & Multiple-Byte Manipulation

19 Arithmetic Instructions (1)
C Z Addition ADD sX, sY sX <= sX + sY ADD sX, KK sX <= sX + KK ADDC sX, sY sX <= sX + sY + CARRY ADDC sX, KK sX <= sX + KK + CARRY IMM, DIR

20 Perform the following operation in the assembly language of PicoBlaze
Questions Perform the following operation in the assembly language of PicoBlaze Add two 3-byte numbers X=(x2, x1, x0) and Y=(y2, y1, y0), stored originally in registers (s2, s1, s0) and (s5, s4, s3), accordingly.

21 Answer x0 EQU s0 x1 EQU s1 x2 EQU s2 y0 EQU s3 y1 EQU s4 y2 EQU s5
ADD x0, y0 ADDC x1, y1 ADDC x2, y2

22 Arithmetic Instructions (2)
C Z Subtraction SUB sX, sY sX <= sX – sY SUB sX, KK sX <= sX – KK SUBC sX, sY sX <= sX – sY – CARRY SUBC sX, KK sX <= sX – KK – CARRY IMM, DIR

23 Perform the following operation in the assembly language of PicoBlaze
Questions Perform the following operation in the assembly language of PicoBlaze Perform the subtraction X=X-Y, where X=(x2, x1, x0) and Y=(y2, y1, y0), and these variables are originally stored in registers (s2, s1, s0) and (s5, s4, s3), accordingly.

24 Answer x0 EQU s0 x1 EQU s1 x2 EQU s2 y0 EQU s3 y1 EQU s4 y2 EQU s5
SUB x0, y0 SUBC x1, y1 SUBC x2, y2

25 Shifts & Rotations

26 Edit instructions - Shifts
*All shift instructions affect Zero and Carry flags

27 Edit instructions - Rotations
*All rotate instructions affect Zero and Carry flags

28 Perform the following operation in the assembly language of PicoBlaze
Questions Perform the following operation in the assembly language of PicoBlaze Perform the left shift (C, X) <= X << 1, where X = (x2, x1, x0) is stored in registers (s2, s1, s0), and the most significant bit of X is shifted into the carry flag.

29 Answer x0 EQU s0 x1 EQU s1 x2 EQU s2 SL0 x0 SLA x1 SLA x2

30 and Program Flow Instructions
Test, Compare, and Program Flow Instructions

31 Test and Compare Instructions
C Z TEST TEST sX, sY sX and sY => none TEST sX, KK sX and KK => none COMPARE COMP sX, sY sX – sY => none COMP sX, KK sX – KK => none IMM, DIR C = odd parity of the result IMM, DIR

32 Program Flow Control Instructions (1)
JUMP AAA PC <= AAA JUMP C, AAA if C=1 then PC <= AAA else PC <= PC + 1 JUMP NC, AAA if C=0 then PC <= AAA else PC <= PC + 1 JUMP Z, AAA if Z=1 then PC <= AAA else PC <= PC + 1 JUMP NZ, AAA if Z=0 then PC <= AAA else PC <= PC + 1

33 If-else statement C Assembly language if (s0 == s1) { ………. } else {
………..

34 If-else statement C Assembly language if (s0 == s1) { COMP s0, s1 ……….
} else { ……….. COMP s0, s1 JUMP NZ, else_branch ……….. JUMP if_done else_branch: if_done:

35 Switch statement C Assembly language switch (s0) { case value_1: ……….
break; case value_2: case value_3: default: }

36 Switch statement C Assembly language switch (s0) { case value_1: ……….
COMP s0, value_1 JUMP NZ, case_2 ………. JUMP case_done case_2: COMP s0, value_2 JUMP NZ, case_3 case_3: COMP s0, value_3 JUMP NZ, default default: case_done: switch (s0) { case value_1: ………. break; case value_2: case value_3: default: }

37 For loop C Assembly language for(i=MAX, i>=0, i--) { …………… }

38 For loop C Assembly language for(i=MAX; i>0; i--) { …………… }
LOAD s0, MAX for_loop: ………. SUB s0, 1 JUMP NZ, for_loop for(i=MAX; i>=0; i--) { …………… } LOAD s0, MAX for_loop: ………. SUB s0, 1 JUMP NC, for_loop

39 Subroutines

40 Subroutine-Related Instructions
CALL AAA TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA CALL C | Z , AAA if C | Z =1 then else PC <= PC + 1 CALL NC | NZ , AAA if C | Z =0 then

41 Subroutine-Related Instructions
RET PC <= STACK[TOS] + 1; TOS <= TOS - 1 RET C | Z if C | Z =1 then else PC <= PC + 1 RET NC | NZ if C | Z =0 then

42 Subroutine Call Flow

43 Instructions Involving
Data Memory

44 Data Movement Instructions
Involving Data Memory C Z - - STORE STORE sX, KK RAM(KK) <= sX STORE sX, sY RAM((sY)) <= sX DIR, IND - - FETCH FETCH sX, KK sX <= RAM(KK) FETCH sX, (sY) sX <= RAM((sY) DIR, IND

45 Example 1: Clear Data RAM of the size of 64 bytes
;========================================================= ; routine: clr_data_mem ; function: clear data ram ; temp register: data, s2 RAM_SIZE EQU 0x ; size of RAM = 64 clr_data_mem: load s2, RAM_SIZE ; unitize loop index to 64 load s0, 0x00 clr_mem_loop: sub s2, 0x ;dec loop index store s0, (s2) jump nz, clr_mem_loop ;repeat until s2=0 ret

46 Input/Output Instructions

47 Input/Output Instructions
C Z - - DIR, IND IN IN sX, KK sX <= PORT(KK) IN sX, (sY) sX <= PORT((sY)) OUT OUT sX, KK PORT(KK) <= sX OUT sX, (sY) PORT((sY)) <= sX - - DIR, IND

48 Example 2: Clear External RAM of the size of 64 bytes
;========================================================= ; routine: clr_ext_mem ; function: clear data ram ; temp register: data, s2 RAM_SIZE EQU 0x ; size of RAM = 64 clr_ext_mem: load s2, RAM_SIZE ; unitize loop index to 64 load s0, 0x00 clr_mem_loop: sub s2, 0x ;dec loop index out s0, (s2) jump nz, clr_mem_loop ;repeat until s2=0 return

Download ppt "Lecture 16 PicoBlaze Instruction Set & Assembler Directives"

Similar presentations

George Mason University ECE 448 – FPGA and ASIC Design with VHDL ECE 448 Lecture 12 Sorting Example.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL ECE 448 Lecture 12 Sorting Example.
George Mason University Timing Analysis ECE 545 Lecture 8a.

George Mason University Timing Analysis ECE 545 Lecture 8a.
Review of Blackfin Syntax Moves and Adds 1) What we already know and have to remember to apply 2) What we need to learn.

Review of Blackfin Syntax Moves and Adds 1) What we already know and have to remember to apply 2) What we need to learn.
ICS312 Set 3 Pentium Registers. Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures.

ICS312 Set 3 Pentium Registers. Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures.
Algorithmic State Machine (ASM) Charts

Algorithmic State Machine (ASM) Charts
George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,
ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.
George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.
ECE 448 – FPGA and ASIC Design with VHDL Lecture 13 PicoBlaze I/O & Interrupt Interface.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 13 PicoBlaze I/O & Interrupt Interface.
ECE 448 – FPGA and ASIC Design with VHDL Lecture 15 External SRAM.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 15 External SRAM.
1 Kadlec MAPLD05/P149 Floating Point Controller as PicoBlaze Network on Single Spartan 3 FPGA Jiri Kadlec 1, Roger Gook 2 1 Institute of Information Theory.

1 Kadlec MAPLD05/P149 Floating Point Controller as PicoBlaze Network on Single Spartan 3 FPGA Jiri Kadlec 1, Roger Gook 2 1 Institute of Information Theory.
Lecture 9 RTL Design Methodology Sorting Example.

Lecture 9 RTL Design Methodology Sorting Example.
ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.
ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.

ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.
Introduction to Experiment 7 Sorting Using PicoBlaze ECE 448 Spring 2010.

Introduction to Experiment 7 Sorting Using PicoBlaze ECE 448 Spring 2010.
The FPX KCPSM Module Exercise 1 Henry Fu The FPX KCPSM Module Exercise: Network Data Encryption / Decryption Using ROT13 Algorithm Henry Fu Washington.

The FPX KCPSM Module Exercise 1 Henry Fu The FPX KCPSM Module Exercise: Network Data Encryption / Decryption Using ROT13 Algorithm Henry Fu Washington.
Introduction to Experiment 6 Internal FPGA Memories, Pseudo Random Number Generator, Advanced Testbenches ECE 448 Spring 2009.

Introduction to Experiment 6 Internal FPGA Memories, Pseudo Random Number Generator, Advanced Testbenches ECE 448 Spring 2009.
ECE 448 – FPGA and ASIC Design with VHDL George Mason University Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL.

ECE 448 – FPGA and ASIC Design with VHDL George Mason University Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL.
ECE 265 Midterm Review 12/1/2015 1 ECE265. Administrivia  The grade for quiz 3 was not entered into to Carmen before I handed them back.  I realize.

ECE 265 Midterm Review 12/1/ ECE265. Administrivia  The grade for quiz 3 was not entered into to Carmen before I handed them back.  I realize.
Lecture 5 Block Diagrams Modes of Operation of Block Ciphers.

Lecture 5 Block Diagrams Modes of Operation of Block Ciphers.

Similar presentations

Ads by Google