Presentation is loading. Please wait.

Presentation is loading. Please wait.

Retiming Scan Circuit To Eliminate Timing Penalty

Published byHumberto Ashbrook Modified over 9 years ago

Similar presentations

Presentation on theme: "Retiming Scan Circuit To Eliminate Timing Penalty"— Presentation transcript:

1 Retiming Scan Circuit To Eliminate Timing Penalty
Ozgur Sinanoglu NYU - AD Vishwani D. Agrawal Auburn University The slide guide is available in the following file: slidesV10.1.ppt: PowerPoint, version 2003 format.

2 Scan Insertion Sequential test generation Sequential Circuit
Combinational Sequential test generation Combinational Circuit Sequential Circuit Flip-flops converted to fully accessible scan cells Bring the circuit to any state Observe the state any time To deal with the sequentiality problem, one widely utilized DfT approach scan insertion. With the late addition of Intel, any chip design company is utilizing scan insertion today. The idea is adding some multiplexer logic to convert registers into fully accessible scan elements during test so that with shift operations desired stimulus can be loaded into the registers while their content can be unloaded for observation. However,still the number of possible patterns is exponential in the number of registers, which approaches one M today. Scan cells controlled and observed through shift operations MUX Flip-flops

3 Scan Based Test Can select: Functional input Scan input MUX D Q
Automatic Test Equipment Automatic Test Equipment Test application: Circuit Under Test Loading stimulus Capturing response Unloading response F_out Testers typically have multiple channels; however, the more the channels, the costlier. But multitude of channels enables multiple scan chains. Instead of having one long scan chain, we break it into multiple shorter scan chains, so the load/unload operations take fewer cycles. Scan MUX F_in MUX D Q Can select: Functional input Scan input S_out S_in Scan cell Scan_en clk

4 Scan Multiplexer Scan multiplexers enable full access to registers during test Sequential test generation → combinational test generation Test generation complexity, test quality, debugging benefits Combo path F_out Scan MUX MUX D Q F_in MUX D Q S_out S_in Scan cell As designs are getting more complex and new defect types are emerging due to reduced feature sizes, test will become only more challenging and the answer is modular testing due to all the benefits it offers. Scan_en clk Scan delay = (Fanout + MUX) delay on functional paths  performance degradation (slower chip!) Remedy: Partial Scan? Test generation complexity!

5 Earlier Work: Scan Cell Transformation
Move the scan MUX off the critical path Additionally, 1 FF and 1 MUX inserted per transformation Transformation applied on only critical path sinks MUX delay moved elsewhere D Q Scan_en S_in F_in S_out F_out original MUX Before transformation D Q S_in F_in S_out F_out original Scan_en shadow MUX Sel_shadow After transformation longer shorter As designs are getting more complex and new defect types are emerging due to reduced feature sizes, test will become only more challenging and the answer is modular testing due to all the benefits it offers. Sinanoglu, “Eliminating Performance Penalty of Scan,” VLSI Design 2012

6 Earlier Work: Scan Cell Transformation
Scan penalty: MUX-delay + fanout-delay Performance saving by this approach (best case): MUX-delay - fanout-delay (not entire scan penalty) D Q Scan_en S_in F_in S_out F_out original MUX Before transformation D Q S_in F_in S_out F_out original Scan_en shadow MUX Sel_shadow After transformation longer shorter As designs are getting more complex and new defect types are emerging due to reduced feature sizes, test will become only more challenging and the answer is modular testing due to all the benefits it offers. Sinanoglu, “Eliminating Performance Penalty of Scan,” VLSI Design 2012

7 Scan Operations with Transformed Cells
Combinational Logic CAPTURE: Scan-en = 0 Sel_shadow = 1 D Q D Q S_out original original Scan_en D Q D Q shadow S_in original Scan_en Sel_shadow Scan_en 3-bit scan chain fragment; middle cell transformed

8 Scan Operations with Transformed Cells
Combinational Logic D Q D Q S_out original original Scan_en D Q D Q shadow S_in original Scan_en Sel_shadow Scan_en 3-bit scan chain fragment; middle cell transformed FIRST SHIFT: Scan-en = 1 Sel_shadow = 0

9 Scan Operations with Transformed Cells
Combinational Logic D Q D Q S_out original original Scan_en D Q D Q shadow S_in original Scan_en Sel_shadow Scan_en 3-bit scan chain fragment; middle cell transformed OTHER SHIFTS: Scan-en = 1 Sel_shadow = 1

10 Scan Operations with Transformed Cells
Combinational Logic D Q D Q S_out original original Scan_en D Q D Q shadow S_in original Scan_en Sel_shadow Scan_en 3-bit scan chain fragment; middle cell transformed Same scan capabilities  Same test time, coverage, etc.

11 Proposed: Retiming Scan Circuit
Retiming in general: Moving FFs across combinational logic Functionality of a synchronous circuit unchanged D Q Combinational Logic Combinational Logic Retiming D Q D Q Proposed solution: Apply retiming across scan multiplexer at the critical path sinks Apply retiming across scan fanout at the critical path origins Save entire scan penalty C. E. Leiserson, F. Rose, and J. B. Saxe, “Optimizing Synchronous Circuits by Retiming,” Caltech Conf. on VLSI, 1983

12 Proposed: Retiming Scan Circuit
F_out D Q Critical path D Q F_in S_out S_in S_in F_in D Q Critical path Scan_en Scan_en_del Scan_en Select between current func/scan input based on current scan-en Select between registered func/scan input based on registered scan-en

13 Proposed: Retiming Scan Circuit
F_out D Q Critical path D Q F_in S_out S_in Critical path Scan_en D Q D Q F_in S_in D Q Scan_en_del Select between current func/scan input based on current scan-en D Q Scan_en Select between registered func/scan input based on registered scan-en Scan_en_del shared

14 Proposed: Retiming Scan Circuit
F_out D Q Critical path D Q F_in S_out S_in Critical path Scan_en D Q D Q F_in S_in D Q Scan_en_del Identical functionality Both normal & scan modes D Q MUX delay transferred forward Best case saving: MUX delay Scan_en Scan_en_del shared

15 Proposed: Retiming Scan Circuit
Critical path F_out D Q D Q S_out F_in original S_in D Q Scan_en_del shadow Scan enable D Q clock 4 4 2 3 1 Scan_en Scan_en_del Impact on test application (stuck-at): Loaded stimulus reflects from shadow FF Response captured in original FF First shift from original FF Subsequent shifts from shadow FF

16 Proposed: Retiming Scan Circuit
Critical path F_out D Q D Q S_out F_in original S_in D Q Scan_en_del shadow Scan enable D Q clock 5 5 2 3 4 1 Scan_en Scan_en_del Impact on test application (LOC-based): Loaded stimulus reflects from shadow FF Launch from original FF Capture in original FF First shift from original FF Subsequent shifts from shadow FF

17 Proposed: Retiming Scan Circuit
Critical path F_out D Q D Q S_out F_in original S_in D Q Scan_en_del shadow Scan enable D Q clock 5 5 2 3 4 1 Scan_en Scan_en_del Impact on test application (LOS-based): Loaded stimulus reflects from shadow FF Shift-based launch from shadow FF Capture in original FF First shift from original FF Subsequent shifts from shadow FF

18 Proposed: Retiming Scan Circuit
Critical path F_out D Q D Q S_out F_in original S_in D Q Scan_en_del shadow D Q Scan_en Scan_en_del Same scan capabilities  Same test time, coverage, etc.

19 Impact on Timing Originally Critical Path: CP CP – 1.0∆MUX s13 s12
All paths within 2∆MUX delays from critical path shown above Originally Critical Path: CP

20 Impact on Timing Originally Critical Path: CP CP – 1.0∆MUX s13 s12
All paths within 2∆MUX delays from critical path shown above Originally Critical Path: CP

21 Impact on Timing Originally Critical Path: CP Trans. #1
CP – 1.0∆MUX s12 s13 CP – 0.8∆MUX CP – 0.5∆MUX s7 s6 s8 s9 CP – 1.7∆MUX s4 s10 CP – 1.0∆MUX CP – 0.3∆MUX All paths within 2∆MUX delays from critical path shown above Originally Critical Path: CP Trans. #1 Critical Path: CP - 0.3∆MUX

22 Impact on Timing Originally Critical Path: CP Trans. #1
CP – 1.0∆MUX s12 s13 CP – 0.8∆MUX CP – 0.5∆MUX s7 s6 s8 s9 CP – 1.7∆MUX CP – 1.3∆MUX s4 s10 CP – 1.0∆MUX CP – 0.3∆MUX All paths within 2∆MUX delays from critical path shown above Originally Critical Path: CP Trans. #1 Critical Path: CP - 0.3∆MUX

23 Impact on Timing Originally Critical Path: CP Trans. #1
CP – 1.0∆MUX s12 s13 CP – 0.8∆MUX CP – 0.5∆MUX s7 s6 s8 s9 CP – 1.7∆MUX CP – 1.3∆MUX s4 s10 CP – 1.0∆MUX All paths within 2∆MUX delays from critical path shown above Originally Critical Path: CP Trans. #1 Critical Path: CP - 0.3∆MUX Trans. #2 Critical Path: CP - 0.5∆MUX

24 Impact on Timing Originally Critical Path: CP Trans. #1
CP – 1.0∆MUX s12 s13 CP – 0.8∆MUX CP – 0.5∆MUX CP – 1.5∆MUX CP – 0.7∆MUX s7 s6 s8 s9 CP – 1.7∆MUX CP – 1.3∆MUX s4 s10 CP – 1.0∆MUX All paths within 2∆MUX delays from critical path shown above Originally Critical Path: CP Trans. #1 Critical Path: CP - 0.3∆MUX Trans. #2 Critical Path: CP - 0.5∆MUX

25 Impact on Timing CP – 1.0∆MUX s12 s13 CP – 0.8∆MUX s7 CP – 1.5∆MUX CP – 0.7∆MUX Already transformed s6 s8 s9 CP – 1.3∆MUX s4 s10 CP – 1.0∆MUX All paths within 2∆MUX delays from critical path shown above Shortened critical path by 0.7 ∆MUX via 3 transformations Originally Critical Path: CP Trans. #1 Critical Path: CP - 0.3∆MUX Trans. #2 Critical Path: CP - 0.5∆MUX Trans. #3 Critical Path: CP - 0.7∆MUX

26 Impact on Timing CP – 1.0∆MUX s12 s13 CP – 0.8∆MUX s7 CP – 1.5∆MUX CP – 0.7∆MUX Already transformed s6 s8 s9 CP – 1.3∆MUX s4 s10 CP – 1.0∆MUX All paths within 2∆MUX delays from critical path shown above Shortened critical path by 0.7 ∆MUX via 3 transformations Limitation: Critical path originating and terminating at the same FF

27 Iterative Application of Transformations

28 Scan Retiming Further D Q D Q D Q D Q D Q F_out F_in S_out S_in
Critical path F_out D Q F_in D Q S_out S_in D Q Scan_en_del D Q S_out F_out S_in F_in Critical path Scan_en_del MUX delay transferred forward Fanout delay transferred backwards Best case saving: Entire scan penalty (= MUX+fanout delay) D Q Scan_en Scan_en_del shared

29 Experimental Results High performance stream-cipher encryption circuits  Higher reductions in critical path delay

30 Conclusions MUX and fanout delay transfer through proposed scan circuit retiming Can eliminate performance penalty of scan Clock paths untouched Retains intact: Test development process (fault coverage, pattern count, etc) Test application process (test time, data volume, etc) Few scan cells transformed  very small area cost

Download ppt "Retiming Scan Circuit To Eliminate Timing Penalty"

Similar presentations

1 ECE734 VLSI Arrays for Digital Signal Processing Chapter 3 Parallel and Pipelined Processing.

1 ECE734 VLSI Arrays for Digital Signal Processing Chapter 3 Parallel and Pipelined Processing.
Advanced ITC Presentation A. Pogiel J. Rajski J. Tyszer.

Advanced ITC Presentation A. Pogiel J. Rajski J. Tyszer.
Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.

Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.
Registers and Counters

Registers and Counters
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.
Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 Scan design techniques J. M. Martins Ferreira FEUP / DEEC - Rua.

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 Scan design techniques J. M. Martins Ferreira FEUP / DEEC - Rua.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
Assume array size is 256 (mult: 4ns, add: 2ns)

Assume array size is 256 (mult: 4ns, add: 2ns)
Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.

Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.
Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock Priyadharshini Shanmugasundaram Vishwani D. Agrawal.
X-Compaction Itamar Feldman. Before we begin… Let’s talk about some DFT history: Design For Testability (DFT) has been around since the 1960s. The technology.

X-Compaction Itamar Feldman. Before we begin… Let’s talk about some DFT history: Design For Testability (DFT) has been around since the 1960s. The technology.
1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.

1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.
HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ 07974.

HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ
Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher.

Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher.
Vishwani D. Agrawal James J. Danaher Professor

Vishwani D. Agrawal James J. Danaher Professor
HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ 07974.

HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ
Logic and Computer Design Fundamentals Registers and Counters

Logic and Computer Design Fundamentals Registers and Counters
Spring 07, Apr 5 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Retiming Vishwani D. Agrawal James J. Danaher Professor.

Spring 07, Apr 5 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Retiming Vishwani D. Agrawal James J. Danaher Professor.
Chapter 7 - Part 2 1 CPEN 315 - Digital System Design Chapter 7 – Registers and Register Transfers Part 2 – Counters, Register Cells, Buses, & Serial Operations.

Chapter 7 - Part 2 1 CPEN Digital System Design Chapter 7 – Registers and Register Transfers Part 2 – Counters, Register Cells, Buses, & Serial Operations.

Similar presentations

Ads by Google