1. Step 1: State Diagram

2. Step 2: Next State Table

3. Step 3 Flip-Flop Transition Table

4. Step 4: Karnaugh Maps

5. Step 5 and Step 6 Logic Expressions and Counter Implementation
CLK Q0 Q1 Q2

6. Counter Decoding

7. Counter Applications Digital Clock

8. Logic Symbols

9. 2-bit Asynchronous Binary Counter Using VHDL
The clock will be input C.
FF0 the first Flip-flop
FF1 the second flip-flop

10. 2-bit Asynchronous Binary Counter Using VHDL
entity TwoBitCounter is
port(clock: in std_logic; Qa, Qb: buffer std_logic);
end entity TwoBitCounter;
architecture CounterBehavior of TwoBitCounter is
component JKFlipFlop is
port( J, K, Clock: in std_logic; Q, Qnot: inout std_logic);
end component JKFlipFlop;

11. 2-bit Asynchronous Binary Counter Using VHDL
signal I: std_logic;
begin
I <= ‘1’;
FF0:JKFlipFlop port map (J=>I, K=>I, Clock =>clock, Qnot=>Qnot, Q=>Qa);
FF1:JKFlipFlop port map (J=>I, K=>I, Clock=>Qnot, Q=>Qb);
end architecture CounterBehavior;

12. Asynchronous Truncated Counters
To truncate a counter a clear function must be added to the J-K flip-flop
component JKFlipFlopClear is
port( J, K, Clock, Clr: in std_logic; Q, Qnot: inout std_logic);
end component JKFlipFlopClear

13. Asynchronous Truncated Counters Example 9-11
Asynchronous MOD6 (0,1,..5) JK flip-flop with clear
library ieee;
use ieee.std_logic_1164.all;
entity ModSixCounter is
port(clock: in std_logic; Clr: in std_logic; Q0, Q1, Q2: buffer std_logic);
end entity ModSixCounter;

14. Asynchronous Truncated Counters Example 9-11
architecture CounterBehavior of ModSixCounter is
signal Clear: std_logic;
component JKFlipFlopClear is
port (J, K, Clr, Clock: in std_logic; Q, Qnot: inout std_logic);
end component JKFlipFlopClear;
signal I: std_logic;
begin
I <= ‘1’; Clear <= not (Q1 and Q2);
FF0: JKFlipFlopClear port map (J=>I, K=>I, Clr=>Clear, Clock =>clock, Q=>Q0);
FF1: JKFlipFlopClear port map (J=>I, K=>I, Clr=>Clear, Clock=>Q0, Q=>Q1);
FF2: JKFlipFlopClear port map (J=>I, K=>I, Clr=>Clear, Clock=>Q1, Q=>Q2);
end architecture CounterBehavior;

15. Synchronous Counters in VHDL
Synchronous refers to events that occur simultaneously
For synchronous counters all flip-flops are clocked at the same time using the same clock pulse
An example in VHDL would be to use the J-K flip-flop defined as a component then have it clocked using the same clock pulse
Figure 9-13

16. Synchronous Counters in VHDL
entity FourBitSyncCounter is
port( I, clock: in std_logic; Q0, Q1, Q2, Q3: buffer std_logic);
end entity FourBitSyncCounter
architecture CounterBehavior of FourBitSyncCounter is
signal S0, S1, S2: std_logic;
component JKFlipFlop is
port(J, K, Clock: in std_logic;Q, Qnot inout std_logic);
end component JKFlipFlop

17. Synchronous Counters in VHDL
begin
FF0: JKFlipFlop port map (J=>I, K=>I, Clock=>clock, Q=>Q0);
S0<= Q0;
FF1: JKFlipFlop port map (J=>S0, K=>S0, Clock=>clock, Q=>Q1);
S1 <= Q0 and Q1;
FF2: JKFlipFlop port map (J=>S1, K=>S1, Clock=>clock, Q=>Q2);
S2 <= Q0 and Q1 and Q2;
FF3: JKFlipFlop port map (J=>S2, K=>S2, Clock=>clock, Q=>Q3);
end architecture CounterBehavior

18. 3-Bit Gray Code Counter Example 9-13

19. 3-Bit Gray Code Counter Example 9-13
library ieee;
use ieee.std_logic_1164.all;
entity StateCounter is
port(clock: in std_logic; Q: buffer std_logic_vector(0 to 2) );
end entity StateCounter;

20. 3-Bit Gray Code Counter Example 9-13
architecture CounterBehavior of StateCounter is
begin
process (Clock)
if Clock = ‘1’ and Clock’ event then
case Q is
when “000” => Q <= “010”;
when “010” => Q <= “110”;
when “110” => Q <= “100”;
when “100” => Q <= “101”;
when “101” => Q <= “001”;
when “001” => Q <= “000”;
when others => Q <= “000”;
end case;
end if;
end process;
end architecture CounterBehavior;

21. End of Chapter 9

22. Shift Registers
Chapter 10

23. Basic Shift Register Functions
Data Storage
Data Movement
D flip-flops are use to store and move data

24. Basic Shift Register Functions

25. Serial in/Serial out Shift Registers
CLK
Serial in
Serial Out

26. Serial in/Serial out Shift Registers

27. 5-Bit Serial Shift Register Example 10-1

28. 8-bit Shift Register

29. Serial in/Parallel out shift registers
After 4 clock pulses, 0110

30. 8-bit Serial in/Parallel Out

31. Timing Diagram for 8-bit Serial in/Parallel Out
CLR’
Data In QA QB QC QD QE QF QG QH
CLK

32. 4-Bit Parallel in/ Serial out Shift Register

33. 4-Bit Parallel in/ Serial out Shift Register Example 10-3

34. 8-bit Parallel Load Shift Resister

35. Timing Diagram for 8-bit Parallel Load Shift Resister
Loaded
Output
Shift/Load’
Output D0 D1 D2 D3 D4 D5 D6 D7
CLK

36. Parallel in/ Parallel out Shift Register

37. Bidirectional Shift Registers
Data can be shifted left
Data can be shifted right
A parallel load maybe possible
74HC194 is an bidirectional universal shift register

38. Bidirectional Shift Registers Example 10-4

39. 74194 data table _____ | MODE | | SERIAL | PARALLEL | OUTPUTS
CLEAR | S1 S0 | CLK | LEFT RIGHT | A B C D | QA QB QC QD
| | | | |
| X X | X | X X | X X X X |
| X X | | X X | X X X X | QA0 QB0 QC0 QD0
| | POS | X X | a b c d | a b c d
| | POS | X | X X X X | 1 QAn QBn QCn
| | POS | X | X X X X | 0 QAn QBn QCn
| | POS | X | X X X X | QBn QCn QDn 1
| | POS | X | X X X X | QBn QCn QDn 0
| | X | X X | X X X X | QA0 QB0 QC0 QD0

40. 74194

41. 74194 parallel load
CLR’ S1 S0 QA QB QC QD SR SL A B C D
CLK

42. 74194 shift right
CLR’ S1 S0 QA QB QC QD SR SL A B C D
CLK

43. 74194 shift left
CLR’ S1 S0 QA QB QC QD SR SL A B C D
CLK

44. Johnson Counter
CLK Q0 Q1 Q2 Q3

45. Ring Counter
CLK Q0 Q1 Q2 Q3

46. Shift Register Application

47. UART Universal Asynchronous Transmitter

48. Logic Symbols with dependency notation

49. VHDL Code for a Positive-edge Triggered D Flip-flop
D flip-flop that will be used as a component.
library ieee;
use ieee.std_logic_1164.all;
entity DFlipFlop is
port( D, clock: in std_logic; Q, Qnot: inout std_logic);
end entity DFlipFlop;

50. VHDL Code for a Positive-edge Triggered D Flip-flop continued
architecture FlipFlopBehavior of DFlipFlop is
begin
process(D, Clock) is
wait until rising_edge (clock);
if D = ‘1’ then
Q <=‘1’
else
Q <=‘0’
end if;
end process;
Qnot <= not Q;
end architecture FlipFlopBehavior;

51. 4-Bit Serial in/Serial out Shift Registers Using VHDL Example 10-7
library ieee;
use ieee.std_logic_1164.all;
entity SISOReg is
port( I, clock: in std_logic; Qout: buffer std_logic);
end entity SISOReg;

52. 4-Bit Serial in/Serial out Shift Registers Using VHDL Example 10-7
architecture ShiftRegBehavior of SISOReg is
signal Q0, Q1, Q2: std_logic;
component DFlipFlop is
port (D, Clock: in std_logic; Q, Qnot: inout std_logic);
end component DFlipFlop;
begin
FF0: DFlipFlop port map (D=>I, Clock =>clock, Q=>Q0);
FF1: DFlipFlop port map (D=>Q0, Clock=>clock, Q=>Q1);
FF2: DFlipFlop port map (D=>Q1, Clock=>clock, Q=>Q2);
FF3: DFlipFlop port map (D=>Q2, Clock=>clock, Q=>Qout);
end architecture ShiftRegBehavior;

53. 4-Bit Serial in/Parallel out Shift Registers Using VHDL Example 10-8
library ieee;
use ieee.std_logic_1164.all;
entity SIPOReg is
port( I, clock: in std_logic; Q0, Q1, Q2, Q3: buffer std_logic);
end entity SIPOReg;
Defined as an output.

54. 4-Bit Serial in/Parallel out Shift Registers Using VHDL Example 10-8
architecture ShiftRegBehavior of SIPOReg is
signal Q0, Q1, Q2: std_logic;
component DFlipFlop is
port (D, Clock: in std_logic; Q, Qnot: inout std_logic);
end component DFlipFlop;
begin
FF0: DFlipFlop port map (D=>I, Clock =>clock, Q=>Q0);
FF1: DFlipFlop port map (D=>Q0, Clock=>clock, Q=>Q1);
FF2: DFlipFlop port map (D=>Q1, Clock=>clock, Q=>Q2);
FF3: DFlipFlop port map (D=>Q2, Clock=>clock, Q=>Qout);
end architecture ShiftRegBehavior;

55. Parallel in/Serial out Shift Registers
function ShiftLoad (A, B, C,: in std_logic) return std_logic is
begin
return ((A and B) or (not B and C));
end function ShiftLoad;

56. Parallel in/Serial out Shift Registers Example 10-9
library ieee;
use ieee.std_logic_1164.all;
entity PISOReg is
port( SL,D0,D1,D2,D3, clock: in std_logic; Qout: buffer std_logic);
end entity PISOReg;

57. Parallel in/Serial out Shift Registers Example 10-9
architecture ShiftRegBehavior of PISOReg is
function ShiftLoad (A, B, C: in std_logic ) return std_logic is
begin
return (( A and B ) or ( not B and C ));
end function ShiftLoad;
signal S1, S2, S3, Q0, Q1, Q2: std_logic;
component DFlipFlop is
port (D, Clock: in std_logic; Q, Qnot: inout std_logic);
end component DFlipFlop;
SL1: S1 <= ShiftLoad (Q0, SL, D1);
SL2: S2 <= ShiftLoad (Q1, SL, D2);
SL3: S3 <= ShiftLoad (Q2, SL, D3);
FF0: DFlipFlop port map (D=>D0, Clock =>clock, Q=>Q0);
FF1: DFlipFlop port map (D=>S1, Clock=>clock, Q=>Q1);
FF2: DFlipFlop port map (D=>S2, Clock=>clock, Q=>Q2);
FF3: DFlipFlop port map (D=>S3, Clock=>clock, Q=>Qout);
end architecture ShiftRegBehavior;

58. Bidirectional Shift Registers in VHDL
library ieee;
use ieee.std_logic_1164.all;
entity BidirectionalCtr
port(RL, I, clock: in std_logic; Q0, Q1, Q2, Q3: buffer std_logic);
end entity BidirectionalCtr;

59. Bidirectional Shift Registers in VHDL
architecture ShiftRegBehavior of Bidirectional is
function RightLeft(A, B, C:in std_logic) return std_logic is
begin
return ((A and B) or (not B and C));
end function RightLeft;
signal S0, S1, S2, S3: std_logic;
component DFlipFlop is
port( D, Clock: in std_logic; Q, Qnot: inout std_logic);
end component DFlipFlop;

60. Bidirectional Shift Registers in VHDL
begin
SL0: S0 <= RightLeft(I, RL, Q1);
SL1: S1 <= RightLeft(Q0, RL, Q2);
SL2: S2 <= RightLeft(Q1, RL, Q3);
SL3: S3 <= RightLeft(Q2, RL, I);
FF0: DFlipFlop port map (D=>S0, Clock=>clock, Q=>Q0);
FF1: DFlipFlop port map (D=>S1, Clock=>clock, Q=>Q1);
FF2: DFlipFlop port map (D=>S2, Clock=>clock, Q=>Q2);
FF3: DFlipFlop port map (D=>S3, Clock=>clock, Q=>Q3);
end architecture ShiftRegBehavior;

61. End of Chapter 10

62. Traffic Light Using VHDL Chapter 7

63. Block Diagram of the Traffic Light Controller. Figure 7--22

64. Traffic Light Sequence. Figure 7--23

65. Traffic Light VHDL Code Figure 7--23
library ieee;
use ieee.std_logic_1164.all;
entity TrafficLight is
port( S: in std_logic_vector (0 to 1); Main, Side: out natural range 0 to 7 ;
Long, Short: out std_logic );
end entity TrafficLight;

66. Traffic Light VHDL Code Figure 7--23
architecture Behavior of TrafficLight is
type StatesType is (FirstState, SecondState, ThirdState, ForthState);
signal State, NextState: StatesType := FirstState;
begin
ReadState: process (S)
case S is
when “00” => State <=FirstState;
when “01” => State <=SecondState;
when “11” => State <=ThirdState;
when “10” => State <=FourthState;
when others => State <=FirstState;
end case;
end process ReadState;

67. Traffic Light VHDL Code Table 7-5, Page 430
State Inputs
S0 S1
Light Outputs
Main0 Main1 Main2 Side0 Side1 Side2
Trigger Outputs
Long Short
0 0
0 1
1 1
StateDiagram: process (State)
begin
case State is
when FirstState => Main <= 2#001#; Side <= 2#100#; Long <= ‘1’; Short <=‘0’;
when SecondState => Main <= 2#010#; Side <= 2#100#; Long <= ‘0’; Short <=‘1’;
when ThirdState => Main <= 2#100#; Side <= 2#001#; Long <= ‘1’; Short <=‘0’;
when FourthState => Main <= 2#100#; Side <= 2#010#; Long <= ‘0’; Short <=‘1’;
end case;
end process StateDiagram;
end architecture Behavior;

68. Traffic Light Using VHDL Chapter 8

69. Timing of Traffic Light Figures 8-70 and 8-71, Pages 492-3

70. Timing of Traffic Light Figure 8-71, Page 493
library ieee, work;
use ieee.std_logic_1164.all;
entity FrequencyDivider is
port( Clock: in std_logic; Fout: buffer std_logic );
end entity FrequencyDivider;

71. Timing of Traffic Light
architecture FreqDivBehavior of FrequencyDivider is
signal Qa, Qb, Qc, Qd, Qe, Qf, Qg, Qh, Qi, I: std_logic;
component JKFlipFlop is
port ( J, K, Clock: in std_logic; Q, QNot: inout std_logic;
end component JKFlipFlop;
begin
I <= ‘1’;
FF1: JKFlipFlop port map ( J => I, K => I, Clock => CLK, Q =>Qa);
FF2: JKFlipFlop port map ( J => I, K => I, Clock => Qa, Q =>Qb);
FF3: JKFlipFlop port map ( J => I, K => I, Clock => Qb, Q =>Qc);
FF4: JKFlipFlop port map ( J => I, K => I, Clock => Qc, Q =>Qd);
FF5: JKFlipFlop port map ( J => I, K => I, Clock => Qd, Q =>Qe);
FF6: JKFlipFlop port map ( J => I, K => I, Clock => Qe, Q =>Qf);
FF7: JKFlipFlop port map ( J => I, K => I, Clock => Qf, Q =>Qg);
FF8: JKFlipFlop port map ( J => I, K => I, Clock => Qg, Q =>Qh);
FF9: JKFlipFlop port map ( J => I, K => I, Clock => Qh, Q =>Qi);
FF10: JKFlipFlop port map ( J => I, K => I, Clock => Qi, Q =>Fout);
end architecture FreqDivBehavior;

72. Timing of Traffic Light Page 493
library ieee;
use ieee.std_logic_1164.all;
entity Timer is
port( Enable, Clock: in std_logic; SetCount: in integer; Qout: buffer std_logic );
--Enable: Enables counting process
-- Clock: kHz clock driver
-- SetCount: Holds time interval value
-- Qout: Outputs up to value in SetCount
end entity Timer;

73. Timing of Traffic Light Page 494
architecture TimerCount of Timer is
begin
process (Enable, Clock)
variable Cnt: Integer;
if ( Clock’ Event and Clock=‘1’ ) then
if Enable=‘0’ then
Cnt:=0; Qout <=‘1’;
elsif Cnt=SetCount-1 then
Qout <=‘0’
else
Cnt:=Cnt+1;
end if;
end process;
end architecture TimerCount;

74. Traffic Light Using VHDL Chapter 9

75. Block Diagram of the Traffic Light Controller. Figure 9--62

76. Block Diagram of the Sequential Logic. Figure 9--63

77. State Diagram Showing the 2-bit Gray Code Sequence. Figure 9--64

78. Complete VHDL Program for the Traffic Light Controller. Figure 9--66

79. VHDL Code Downloaded into the CPLD. Figure 9--71

80. VHDL Sequential Logic Code Chapter 9 Page 568
library ieee;
use ieee.std_logic_1164.all;
entity SequentialLogic is
port( VS, TL, TS, CLK: in std_logic; S: buffer std_logic_vector (0 to 1) );
end entity SequentialLogic;

81. VHDL Sequential Logic Code Chapter 9 Page 568
architecture LightSequence of SequentialLogic is
begin
process (VS, TL, TS, CLK)
if CLK=‘1’ and CLK’ event then
case S is
when “00” => if (TL=‘1’ or VS=‘0’) then S<=“00”;
elsif (TL=‘0’ and VS=‘1’) then S<=“01”; end if;
when “01” => if (TS=‘1’) then S<=“01”;
elsif (TS=‘0’) then S<=“11”; end if;
when “11” => if (TL=‘1’ and VS=‘1’) then S<=“11”;
elsif (TL=‘0’ or VS=‘0’) then S<=“10”; end if;
when “10” => if (TS=‘1’) then S<=“10”;
elsif (TS=‘0’) then S<=“00”; end if;
when others => S <=“00”;
end case;
end if;
end process;
end architecture LightSequence;

82. Traffic Light Controller Component Block Diagram. Figure 9--72

83. Max 7000 Series Device Block Diagram

84. Max 7000 Series

85. Max 7000 Series

86. Max 7000 Series

87. Max 7000 Series