1. Lecture #24 Page 1 EE 367 – Logic Design Lecture #24 Agenda 1.State Machines Review Announcements 1.n/a

2. Lecture #24 Page 2 State Machines State Machines - there is a basic structure for a Clocked, Synchronous State Machine 1) State Memory(i.e., flip-flops) 2) Next State Logic “G”(combinational logic) 3) Output Logic “F”(combinational logic) we’ll revisit F later… - if we keep this structure in mind while designing digital machines in VHDL, then it is a very straight forward task - Each of the parts of the State Machine are modeled with individual processes - let’s start by reviewing the design of a state machine using a manual method

3. Lecture #24 Page 3 State Machines State Machines “Mealy Outputs” – outputs depend on the Current_State and the Inputs

4. Lecture #24 Page 4 State Machines State Machines “Moore Outputs” – outputs depend on the Current_State only

5. Lecture #24 Page 5 State Machines State Machines - the steps in a state machine design are: 1) Word Description of the Problem 2) State Diagram 3) State/Output Table 4) State Variable Assignment 5) Choose Flip-Flop type 6) Construct F 7) Construct G 8) Logic Diagram

6. Lecture #24 Page 6 State Machines State Machine Example “Sequence Detector” 1) Design a machine by hand that takes in a serial bit stream and looks for the pattern “1011”. When the pattern is found, a signal called “Found” is asserted 2) State Diagram

7. Lecture #24 Page 7 State Machines State Machine Example “Sequence Detector” 3) State/Output Table Current_StateInNext_StateOut (Found) S00S00 1S10 S10S20 1S00 S20S00 1S30 S30S00 1S01

8. Lecture #24 Page 8 State Machines State Machine Example “Sequence Detector” 4) State Variable Assignment – let’s use binary Current_StateInNext_StateOut Q1 Q0 Q1* Q0* Found 0 00 0 00 1 0 10 0 10 1 00 1 0 00 1 00 0 00 1 1 10 1 10 0 00 1 0 01 5) Choose Flip-Flop Type - 99% of the time we use D-Flip-Flops

9. Lecture #24 Page 9 State Machines State Machine Example “Sequence Detector” 6) Construct Next State Logic “F” Q1* = Q1’∙Q0∙In’ + Q1∙Q0’∙In Q0* = Q0’∙In 01 00 Q1 Q0 In 0001 0 1 0 1 2 3 In Q1 0 0 6 7 0 1 4 5 1110 Q0 00 10 Q1 Q0 In 0001 0 1 0 1 2 3 In Q1 0 0 6 7 0 1 4 5 1110 Q0

10. Lecture #24 Page 10 State Machines State Machine Example “Sequence Detector” 7) Construct Output Logic “G” Found = Q1∙Q0∙In 8) Logic Diagram - for large designs, this becomes impractical 00 00 Q1 Q0 In 0001 0 1 0 1 2 3 In Q1 0 1 6 7 0 0 4 5 1110 Q0

11. Lecture #24 Page 11 State Machines in VHDL State Memory - we use a process that updates the “Current_State” with the “Next_State” - we describe DFF’s using (CLK’event and CLK=‘1’) - this will make the assignment on the rising edge of CLK STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') then Current_State <= Next_State; end if; end process; - at this point, we need to discuss State Names

12. Lecture #24 Page 12 State Machines in VHDL State Memory using “User-Enumerated Data Types" - we always want to use descriptive names for our states - we can use a user-enumerated type for this type State_Type is (S0, S1, S2, S3); signal Current_State : State_Type; signal Next_State : State_Type; - this makes our simulations very readable. State Memory using “Pre-Defined Data Types" - we haven’t encoded the variables though, we can either leave it to the synthesizer or manually do it subtype State_Type is BIT_VECTOR (1 downto 0); constant S0 : State_Type := “00”; constant S1 : State_Type := “01”; constant S2 : State_Type := “10”; constant S3 : State_Type := “11”; signal Current_State : State_Type; signal Next_State : State_Type;

13. Lecture #24 Page 13 State Machines in VHDL State Memory with “Synchronous RESET” STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') then if (Reset = ‘1’) then Current_State <= S0;-- name of “reset” state to go to else Current_State <= Next_State; end if; end if; end process; - this design will only observe RESET on the positive edge of clock (i.e., synchronous)

14. Lecture #24 Page 14 State Machines in VHDL State Memory with “Asynchronous RESET” STATE_MEMORY : process (CLK, Reset) begin if (Reset = ‘1’) then Current_State <= S0;-- name of “reset” state to go to elsif (CLK’event and CLK='1') then Current_State <= Next_State; end if; end process; - this design is sensitive to both RESET and the positive edge of clock (i.e., asynchronous)