1. 21.10.02ES Seminar1 Communicating Transaction Processes P.S. Thiagarajan National University of Singapore Joint Work with: Abhik Roychoudhury; ……

2. 21.10.02ES Seminar2 The Main Features To support System Level Design –One Level of Abstraction higher than C, C++, VHDL.. UML-compatible –MSCS + Asynchronous control flow –Based on MSCs (Message Sequence Charts) –Sequence Diagrams

3. 21.10.02ES Seminar3 Why System Level Design? Closer to end-use(r). Less detailed and more architecture-neutral. Easier reuse/adaptaton. Easier to verify. –Safety-critical applications need to be correct. –Catch design errors early. –Coupling with a correct-by-construction synthesis method is an attractive option.

4. 21.10.02ES Seminar4 What is Available? Data flow graphs. Automata of various kinds. Petri nets. State charts. Esterel, Lustre. SDL, UML.

5. 21.10.02ES Seminar5 Why UML-compatible? UML is getting rapidly established as a standard. –Mainly in software engineering projects –Increasingly so in embedded systems domain. Offers a suite of graphical notations: –Multiple views –Behavioral and structural diagrams. –Object orientation.  Reuse, adaptation

6. 21.10.02ES Seminar6 An Idealized Design Flow Requirements Exec. Specifications. Intermediate representation SW/HW Implementation. High Level Description

7. 21.10.02ES Seminar7 Requirements and Exec. Specifications Requirements : Message Sequence Charts (MSCs) Exec. Specifications : –State charts. UML supports both but no clear distinction made. Other Exec. Spec. : –Petri nets, –MPAs (Message Passing Automata), ….

8. 21.10.02ES Seminar8 MSCs Message Sequence Charts: –Describe scenarios. –A finite pattern of interaction between agents (object instances,..). –A story

9. 21.10.02ES Seminar9 Message Sequence Charts rq U1R rq y n U2

10. 21.10.02ES Seminar10 Message Sequence Charts rq U1R rq y n U2

11. 21.10.02ES Seminar11 Message Sequence Charts rq U1R rq y n U2 internal action

12. 21.10.02ES Seminar12 Message Sequence Charts rq U1R rq y n U2 internal actions

13. 21.10.02ES Seminar13 Message Sequence Charts rq U1R rq y n U2

14. 21.10.02ES Seminar14 Message Sequence Charts rq U1R rq y n U2

15. 21.10.02ES Seminar15 Message Sequence Charts rq U1R rq y n U2

16. 21.10.02ES Seminar16 Message Sequence Charts rq U1R rq y n U2

17. 21.10.02ES Seminar17 Message Sequence Charts rq U1R rq y n U2

18. 21.10.02ES Seminar18 Message Sequence Charts rq U1R rq yn U2

19. 21.10.02ES Seminar19 Message Sequence Charts rq U1R rq y n U2

20. 21.10.02ES Seminar20 Message Sequence Charts rq U1R rq y n U2

21. 21.10.02ES Seminar21 Message Sequence Charts rq U1R rq y n U2

22. 21.10.02ES Seminar22 CTPs Communicating Transaction Processes. An executable spec. mechanism. –Based on MSCs. A network of interacting agents. –Agent’s interaction pattern behavior:  Standard distributed system model –Interaction:  Guarded choice of MSCs.  Transaction schemes.

23. 21.10.02ES Seminar23 Distributed System Models Petri nets Data flow graphs Statecharts Distributed transition systems (many kinds!) Process algebras (CCS, CSP, …)

24. 21.10.02ES Seminar24 PI1 IB1IB2 PI2 I1 B I2 P2

25. 21.10.02ES Seminar25 PI1 IB1IB2 PI2 I1 B I2 P2

26. 21.10.02ES Seminar26 PI1 IB1IB2 PI2 I1 B I2 P2

27. 21.10.02ES Seminar27 PI1 IB1IB2 PI2 I1 B I2 P2

28. 21.10.02ES Seminar28 PI1 IB1IB2 PI2 I1 B I2 P2

29. 21.10.02ES Seminar29 PI1 IB1IB2 PI2 I1 B I2 P2 But the boxes will have internal structure. A complex Transaction Scheme.

30. 21.10.02ES Seminar30 Transaction Scheme waitcount2:= waitcount2 + 1  2data.present & B.free  2data.present &  B.free  I2B req y add data I2B req n I2B   2data.present 

31. 21.10.02ES Seminar31 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free 

32. 21.10.02ES Seminar32 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

33. 21.10.02ES Seminar33 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

34. 21.10.02ES Seminar34 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

35. 21.10.02ES Seminar35 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

36. 21.10.02ES Seminar36 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

37. 21.10.02ES Seminar37 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

38. 21.10.02ES Seminar38 P11 I1  1data.present  no-op  1data.present   1data.present  no-data  1data.present  data  1data.present  P11 Transaction Scheme I1

39. 21.10.02ES Seminar39 Analysis Issues Determine whether a CTP is bounded. Determine if a CTP can deadlock. Determine if a CTP is well-formed.

40. Current Status The CTP Model SMV ES Representation Verilog Analysis Verification Simulation; Synthesis Case Studies Modeling

41. Current Status The CTP Model SMV ES Representation Verilog Analysis Verification Simulation; Synthesis Case Studies Modeling Pankaj Jain Nikhil Jain Kamrul Hasan Talukdar Tran Tuan Anh Ge Zhiguo

42. 21.10.02ES Seminar42 Future Work Add multiple instances of a process. –Object features Add timing constraints. Develop the computational model. –Interactions with environment (sense, actuate) –Computational steps (control law) –Schedulability is a key issue. HW/SW Partitioning; Architectural mapping; Synthesis?