Presentation is loading. Please wait.

Presentation is loading. Please wait.

Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders.

Published byBrian Mauldin Modified over 9 years ago

Similar presentations

Presentation on theme: "Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders."— Presentation transcript:

1 Encoders Module M9.3 Section 6.3

2 Encoders Priority Encoders TTL Encoders

3 Encoders A B I0 I1 I2 I3 4-to-2 Encoder 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 I0 I1 I2 I3 B A

4 Encoders 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 I0 I1 I2 I3 B A Assume only 1 input can be high at any time. A = I1 # I3 B = I2 # I3 I1 I2 I3 I0 B = I2 # I3 A = I1 # I3

5 8-to-3 Encoder 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y2 = I7 # I6 # I5 # I4 Y1 = I7 # I6 # I3 # I2 Y0 = I7 # I5 # I3 # I1

6 encoder.abl MODULE encoder83 TITLE 'Encoder, D. Hanna, 7/15/02' DECLARATIONS " INPUT PINS " I7..I0 PIN 6, 7, 11, 5, 72, 71, 66, 70; " Switch 1..8 " OUTPUT PINS " Y2..Y0 PIN 37, 36, 35 ISTYPE 'com'; " LED 6..8 EQUATIONS Y2 = I7 # I6 # I5 # I4; Y1 = I7 # I6 # I3 # I2; Y0 = I7 # I5 # I3 # I1; END encoder83

7 Priority Encoder 1 0 0 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 1 X X 1 0 0 0 0 0 0 1 0 X X X 1 0 0 0 0 0 1 1 X X X X 1 0 0 0 1 0 0 X X X X X 1 0 0 1 0 1 X X X X X X 1 0 1 1 0 X X X X X X X 1 1 1 1 I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0

8 Priority Encoder 1 0 0 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 1 X X 1 0 0 0 0 0 0 1 0 X X X 1 0 0 0 0 0 1 1 X X X X 1 0 0 0 1 0 0 X X X X X 1 0 0 1 0 1 X X X X X X 1 0 1 1 0 X X X X X X X 1 1 1 1 I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y2 = L7 # L6 # L5 # L4 L7 = I7 L6 = !I7 & I6 L5 = !I7 & !I6 & I5 L4 = !I7 & !I6 & !I5 & I4

9 Priority Encoder 1 0 0 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 1 X X 1 0 0 0 0 0 0 1 0 X X X 1 0 0 0 0 0 1 1 X X X X 1 0 0 0 1 0 0 X X X X X 1 0 0 1 0 1 X X X X X X 1 0 1 1 0 X X X X X X X 1 1 1 1 I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y1 = L7 # L6 # L3 # L2 L7 = I7 L6 = !I7 & I6 L3 = !I7 & !I6 & !I5 & !I4 & I3 L2 = !I7 & !I6 & !I5 & !I4 & !I3 & I2

10 Priority Encoder 1 0 0 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 1 X X 1 0 0 0 0 0 0 1 0 X X X 1 0 0 0 0 0 1 1 X X X X 1 0 0 0 1 0 0 X X X X X 1 0 0 1 0 1 X X X X X X 1 0 1 1 0 X X X X X X X 1 1 1 1 I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y0 = L7 # L5 # L3 # L1 L7 = I7 L5 = !I7 & !I6 & I5 L3 = !I7 & !I6 & !I5 & !I4 & I3 L1 = !I7 & !I6 & !I5 & !I4 & !I3 & !I2 & I1

11 pencoder.abl MODULE pencoder83 TITLE 'Priority Encoder, A. Student, 7/15/02' DECLARATIONS " INPUT PINS " I7..I0 PIN 6, 7, 11, 5, 72, 71, 66, 70; " Switch 1..8 " OUTPUT PINS " Y2..Y0 PIN 37, 36, 35 ISTYPE 'com'; " LED 6..8 VALID PIN 44;" LED 1 " VALID = 1 for valid binary output " INTERMEDIATE NODES " L7..L0 NODE ISTYPE 'com'; " internal vector

12 pencoder.abl (cont’d) EQUATIONS L7 = I7; L6 = !I7 & I6; L5 = !I7 & !I6 & I5; L4 = !I7 & !I6 & !I5 & I4; L3 = !I7 & !I6 & !I5 & !I4 & I3; L2 = !I7 & !I6 & !I5 & !I4 & !I3 & I2; L1 = !I7 & !I6 & !I5 & !I4 & !I3 & !I2 & I1; Y2 = L7 # L6 # L5 # L4; Y1 = L7 # L6 # L3 # L2; Y0 = L7 # L5 # L3 # L1; END pencoder83

13 TTL Encoder 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 GND Vcc 1 2 3 4 5 6 7 A2 A1 E1 E0 GS 0 A0 74LS148 1 X X X X X X X X 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 X X X X X X X 0 0 0 0 0 1 0 X X X X X X 0 1 0 0 1 0 1 0 X X X X X 0 1 1 0 1 0 0 1 0 X X X X 0 1 1 1 0 1 1 0 1 0 X X X 0 1 1 1 1 1 0 0 0 1 0 X X 0 1 1 1 1 1 1 0 1 0 1 0 X 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO Priority Encoder

14

15 68000 Interrupt Logic Peripheral 74148 Encoder 74138 Decoder IP0 IP1 IP2 A0 A1 A2 IRQA 68000 Data Bus IRQ

Download ppt "Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders."

Similar presentations

Adders Module M8.1 Section 6.2. Adders Half Adder Full Adder TTL Adder.

Adders Module M8.1 Section 6.2. Adders Half Adder Full Adder TTL Adder.
1 The 2-to-4 decoder is a block which decodes the 2-bit binary inputs and produces four output All but one outputs are zero One output corresponding to.

1 The 2-to-4 decoder is a block which decodes the 2-bit binary inputs and produces four output All but one outputs are zero One output corresponding to.
Modulo-N Counters Module M10.4 Section 7.2.

Modulo-N Counters Module M10.4 Section 7.2.
5.5 Encoders A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes.

5.5 Encoders A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes.
Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN 0 0 0 0 1 0 YIN 0 0 1 0 0 0 YIN 0 1 1.

Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN YIN YIN
Shift Registers Module M11.1 Section 7.3.

Shift Registers Module M11.1 Section 7.3.
7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.

7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.
Memory Section 7.2. Types of Memories Definitions – Write: store new information into memory – Read: transfer stored information out of memory Random-Access.

Memory Section 7.2. Types of Memories Definitions – Write: store new information into memory – Read: transfer stored information out of memory Random-Access.
Magnitude Comparator Lecture L6.4 Section 6.1.

Magnitude Comparator Lecture L6.4 Section 6.1.
Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.
7-Segment Displays Lecture L6.7 Section 6.5. Turning on an LED.

7-Segment Displays Lecture L6.7 Section 6.5. Turning on an LED.
Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp. 101-106.

Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp
Using State Machines as Control Circuits Lecture L9.4.

Using State Machines as Control Circuits Lecture L9.4.
Multiplier Lecture L7.3 Section 10.4 (p.276) Section 7.3 (Handout)

Multiplier Lecture L7.3 Section 10.4 (p.276) Section 7.3 (Handout)
1 CS 140 Lecture 12 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego.

1 CS 140 Lecture 12 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego.
Multiplexers Lecture L6.4 Section 6.4.

Multiplexers Lecture L6.4 Section 6.4.
CS 140 Lecture 11 Professor CK Cheng 5/09/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,

CS 140 Lecture 11 Professor CK Cheng 5/09/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,
Subtractors Module M8.2 Section 6.2. Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2.

Subtractors Module M8.2 Section 6.2. Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2.
Designing State Machines Lecture L9.2 Handout Section 9.2.

Designing State Machines Lecture L9.2 Handout Section 9.2.
Arbitrary Waveforms Lecture L8.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1.

Arbitrary Waveforms Lecture L8.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.

Similar presentations

Ads by Google