1. GCT Meeting: DTPM Status: Greg Iles1 July 20051 DTPM Fundamentals TPMs 0 to 7 send event data and status and receive control Receive TPM event data Buffer event data, insert checksums and control readout CM receives event data and status and sends control Verify data and send to CM Receive control and forward to fpga c0 for distribution (indirect) FPGAs : i2/i3FPGAs : p3FPGAs : ro, r1 and r3 Send status info to CM Merge status information and record history Receive TPM status data Event dataControlStatus

2. GCT Meeting: DTPM Status: Greg Iles1 July 20052 DTPM Status Rx Data SimTPM Tx Cntrl Verify TPM0 Input (rx) TPM1 Input (rx) TPM7 Input (rx) TPM Buf (p3) TPM0 Data Data DPM Data size FIFO Check & pad Verify TPM1 Data TPM7 Data Mux Data Merge Status from DPM and FIFO buffer levels Event header Chksum (p3) Insert Link0, Ch0 Chksum (i2) Verify Ch0 Verify Ch1 Ser (i2) Tx Evnt Tx Status Tx Evnt Rx Cntrl Chksum (i2)Ser (i3) Insert Link0, Ch1 Insert Link0, Ch1 Insert Link1, Ch1 TPMs 0 to 7 send event data and receive cntrl Conn (xx)ControlBus (c0) WB Comm Readout Sync Cntrl Status FPGA Bypass Duplicate for TPMs 2-6 Duplicate for TPMs 2-6 history Status (all) merge Cntrl (all) respond to cntrl CM receives event data and sends cntrl Bristol : DoneCERN : DoneBristol : PendingCERN: Pending

3. GCT Meeting: DTPM Status: Greg Iles1 July 20053 Progress Progress –20/6: Programmed DTPM FPGAs r0, p3 and i2 via compact flash Would have allowed fake TPM data generated in r0 to be propagated through p3 and into i2. Able to communicate with p3 Unable to communicate with r0 or i2 or any other chip on control bus A. Works OK in simulation. Rather than debug we wait for new control bus. –23/6: Synthesized i3. Sufficient FPGA code to now link to CM –28/6: Simulation of virtual CM-DTPM SerDes links Works well in simulation. –29/6: First iteration of history block (maybe used by TPMs & CM) Needs some additional features

4. GCT Meeting: DTPM Status: Greg Iles1 July 20054 Plan Data –Add verification check to incoming data from TPMs. Links to and from CM and event blocks generated in p3 are protected with error checking.Control –Need to make sure that all units respond in a sensible fashion to TTC control signals (e.g. state machine ought to come out of error on resync).Status –Provide method for storing and merging status (e.g. READY, BUSY, etc) and their origins (e.g. what caused the board to flip into BUSY) Software & Testing –As soon as the new control bus is finished we can start testing. Ideally want the final software access to wishbone slaves in place soon. PS Probably shouldn’t mentions thing like this, however: I thought there was a rough plan to have finished DTPM-CM integration by end of June and TPM-DTPM-CM integration by end of July. Any thoughts......