1. Decoder
Mano Section 4.9 &4.12

2. Schedule 10 2/17 Monday Decoder 11 2/19 Wednesday
Encoder (hw3 is assigned) L
2/20
Thursday
Decoder Experiment 12
2/24
MUX/Three state (data flow versus behavioral) 13
2/26
Catch-up (hw3 is due)
2/27
Random number generator 14
3/3
Test 1

3. Outline
Feedback
Applications
Memory
Decoder
Verilog Modeling

4. Feedback on the labs Tutorial Finish the labs before you leave.
emacs/vi tutorial at the course webpage.
Verilog tutorial
Always start from the textbook (There is usually a section on Verilog at the end of each chapter)
Supplement the textbook with the tutorial from ASIC.
Use the existing sample code as a starting point.
Finish the labs before you leave.

5. Example (1): A Year Year’s Eve Display

6. Example (2): Binary to Octal Conversion
Convert binary information from n input lines to 2n unique output
lines.
This particular circuit take a binary number and convert it to an octal
number.

7. Hardware Implementation

8. Example (3): Organization of Memory Systems

9. AND and NOR Decoders One of which is activated. Each is a combination
leading to a “1”
Take an n-bit address.
Produce 2n outputs,
One of which is activated.
(NOR Decoder)

10. A 2-to-4 decoder with Enable
(typo, should
be a 0)

11. Example (4): Demultiplexer
A Demux is a circuit that receives information from a single
line and directs it to one of 2n possible output lines.

12. Use a 2-to-4 decoder as a Demux
Treat A and B as the selector bits. i.e.
A and B select which bit should receive informraiton.
E is treated as the data line.
(typo, should
be a 0)

13. Example (5): Implement a Full Adder with a Decoder

14. Example (6): Build a Bigger Decoders
Use w to enable either top or bottom decoder.

15. Verilog Modeling

16. Outline 2-to-4 decoder 3-to-8 decoder
Decode24a.v: uses assign statements
3-to-8 decoder
Build from a two 2-to-4 decoder

17. A 2-to-4 decoder with Enable
Program body:
D0=~((~A)&(~B)&(~E))
D1=~((~A)&(B)&(~E))
D2=~((A)&(~B)&(~E))
D3=~((A)&(B)&(~E))
Inputs: A,B, E
Outputs: D0, D1, D2, D3
(typo, should
be a 0)

18. decode24a.v wire is declared in a more “compact” way.
Instead of D0,D1,D2,D3.

19. Decode24a_tb.v Start from full_adder_tb.v
Print out D as a 4 bit number.

20. 3-to-8 decoder in verilog
Module: decode38a.v
Inputs: x,y,w
wires: x,y,w
outputs: D0 to D7
wires:D0 to D7
wire: wb
Program body:
call on two instances of
decode24a I1 wb I2

21. 3-to-8 decoder in verilogwb I2

22. 3-to-8 decoder in verilogwb I2

23. Test Bench for decode38a,.v

24. Optional Slides

25. Basic SRAM and VTC A wordline is used to select the cell
Bitlines are used to perform read and write operations on the cell

26. Cross Coupled Configuration
The cell can only flip its internal state when one of its internal cross VS.
During a read op, we must not disturb its current state.
During a write op, we must force the internal voltage to swing past VS to change a state.

27. 3-to-8 decoder in verilog

28. 3-to-8 decode
Input bits

29. Use a Test Bench to Generate output
Initial statements execute once
starting from time 0.
$monitor: display variable whenever
a value changes.
$time display the simulation time

30. Run functional Simulation

31. Results