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Central Processing Unit

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Presentation on theme: "Central Processing Unit"— Presentation transcript:

1 Central Processing Unit
(Fetch Cycle)

2 Central Processing Unit
FETCH Programming Counter (PC) 1 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Data The value stored in the program counter corresponds to the address of the instruction In memory which is next to be processed. 6 Data 7 Data 8 Data Central Processing Unit

3 Central Processing Unit
FETCH Program Counter (PC) 1 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Data 6 Data For the value to be used in the Program Counter, it is firstly transferred to the Memory Address Register (MAR) Memory Address Register (MAR) 7 Data 1 8 Data Central Processing Unit

4 Central Processing Unit
FETCH Program Counter (PC) 1 Instruction 2 2 Instruction 3 Instruction The program counter is now incremented by +1 so it points to the next instruction. 4 Instruction 5 Data 6 Data Memory Address Register (MAR) 7 Data 1 8 Data Central Processing Unit

5 Central Processing Unit
FETCH Program Counter (PC) 1 Instruction (I1) 2 2 Instruction (I2) 3 Instruction (I3) 4 Instruction (I4) Memory Data Register (MDA) 5 Data 6 Data Memory Buffer Register (MBR) 7 Data Memory Address Register (MAR) 8 Data 1 Control Unit The control unit checks the value in the memory address register before fetching the corresponding address in memory Central Processing Unit

6 Central Processing Unit
FETCH Program Counter (PC) 1 Instruction (I1) 2 2 Instruction (I2) 3 Instruction (I3) 4 Instruction (I4) Memory Data Register (MDA) 5 Data I1 6 Data The fetched instruction is then stored in the MDR Memory Buffer Register (MBR) 7 Data Memory Address Register (MAR) 8 Data 1 Control Unit Central Processing Unit

7 Central Processing Unit
FETCH Program Counter (PC) 2 1 Instruction (I1) 2 Instruction (I2) Current Instruction Register (CIR) 3 Instruction (I3) I1 4 Instruction (I4) The value in the Memory Data Register is transferred to the Current Instruction Register Instruction Register (IR) 5 Data Memory Data Register (MDA) 6 Data I1 7 Data Memory Buffer Register (MBR) 8 Data Memory Address Register (MAR) 1 Control Unit Central Processing Unit

8 Central Processing Unit
FETCH Program Counter (PC) 2 1 Instruction (I1) 2 Instruction (I2) Current Instruction Register (CIR) 3 Instruction (I3) The instruction has been loaded into the CIR and is now ready to be decoded and executed. I1 4 Instruction (I4) Instruction Register (IR) 5 Data Memory Data Register (MDA) 6 Data 7 Data Memory Buffer Register (MBR) 8 Data Memory Address Register (MAR) 1 Control Unit Central Processing Unit

9 Central Processing Unit
FETCH SUMMARY Program Counter Memory Address Register Program Counter + 1 Control Unit Memory Address Register Memory Address Register Instruction I1 Instruction I1 Memory Data Register Memory Data Register Current Instruction Register Central Processing Unit


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